[llvm] [RISCV][WIP] Let RA do the CSR saves. (PR #90819)

[Mikhail Gudim via llvm-commits]

mgudim wrote:

Hi all, just just wanted to give an update on this:

I looked at the xz degradation:

Half of it is due to the fact that since now we have some long live ranges, early-machinelicm doesn't hoist as well as before. This is easy to fix though. If the register pressure for some class exceeds the limit then there will be a spill. If there are live ranges that are live-through entire loop without any uses inside the loop, then these ranges will be spilled first. So basically, I fixed this by ignoring such live-through-no-uses-inside-loop live ranges in `InitRegPressure`.

The other problem is that RA seems to be doing something wrong and I got some extra spills. I hope that can be fixed too.

The biggest problem is that we need to emit CFI directives that tell runtime how to restore ALL callee-saved registers. With my approach I don't know what is the best way to do this. I don't know this CFI stuff very well, so I am hoping someone can give an advise / suggestion. I can only think of having a pass at the very end of the pipeline which tracks what happens to callee-saved registers and emits the directives accordingly. BTW, there is something which looks relevant in `CFIFixup` and `CFIInstrInserter`, but I haven't looked closely yet.

@topperc @preames @mshockwave @wangpc-pp @asb any suggestions how to do this?

https://github.com/llvm/llvm-project/pull/90819