[llvm] [RISCV][GISel] Add calling convention support for half (PR #94110)

[Craig Topper via llvm-commits]

================
@@ -0,0 +1,136 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator \
+; RUN:    -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfh -target-abi ilp32f \
+; RUN:    -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IZFH %s
+
+define half @callee_half_in_regs(half %x) nounwind {
+  ; RV32I-LABEL: name: callee_half_in_regs
+  ; RV32I: bb.1 (%ir-block.0):
+  ; RV32I-NEXT:   liveins: $x10
+  ; RV32I-NEXT: {{  $}}
+  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+  ; RV32I-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
----------------
topperc wrote:

SelectionDAG has this nan-boxing code in `RISCVTargetLowering::splitValueIntoRegisterParts`. I think its only used when f32 is legal.

```
  if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&           
      PartVT == MVT::f32) {                                                      
    // Cast the [b]f16 to i16, extend to i32, pad with ones to make a float      
    // nan, and cast to f32.                                                     
    Val = DAG.getNode(ISD::BITCAST, DL, MVT::i16, Val);                          
    Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Val);                       
    Val = DAG.getNode(ISD::OR, DL, MVT::i32, Val,                                
                      DAG.getConstant(0xFFFF0000, DL, MVT::i32));                
    Val = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);                          
    Parts[0] = Val;                                                              
    return true;                                                                 
  } 
```

https://github.com/llvm/llvm-project/pull/94110