[llvm] [RISCV][GISel] Add calling convention support for half (PR #94110)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 7 09:27:25 PDT 2024
https://github.com/dtcxzyw updated https://github.com/llvm/llvm-project/pull/94110
>From be6c697b8f6a5c1511dd03bf8861968c93a1f040 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Sat, 1 Jun 2024 20:45:24 +0800
Subject: [PATCH 1/3] [RISCV][GISel] Add calling convention support for half
---
.../Target/RISCV/GISel/RISCVCallLowering.cpp | 4 +-
.../RISCV/GISel/RISCVInstructionSelector.cpp | 2 +
.../irtranslator/calling-conv-half.ll | 136 ++++++++++++++++++
3 files changed, 140 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index c18892ac62f24..beee9405de02a 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -340,7 +340,7 @@ static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget,
// supported yet.
if (T->isIntegerTy())
return T->getIntegerBitWidth() <= Subtarget.getXLen() * 2;
- if (T->isFloatTy() || T->isDoubleTy())
+ if (T->isHalfTy() || T->isFloatTy() || T->isDoubleTy())
return true;
if (T->isPointerTy())
return true;
@@ -361,7 +361,7 @@ static bool isSupportedReturnType(Type *T, const RISCVSubtarget &Subtarget,
// supported yet.
if (T->isIntegerTy())
return T->getIntegerBitWidth() <= Subtarget.getXLen() * 2;
- if (T->isFloatTy() || T->isDoubleTy())
+ if (T->isHalfTy() || T->isFloatTy() || T->isDoubleTy())
return true;
if (T->isPointerTy())
return true;
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index da8daa573b89b..a091380e8ce82 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -849,6 +849,8 @@ const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank(
}
if (RB.getID() == RISCV::FPRBRegBankID) {
+ if (Ty.getSizeInBits() == 16)
+ return &RISCV::FPR16RegClass;
if (Ty.getSizeInBits() == 32)
return &RISCV::FPR32RegClass;
if (Ty.getSizeInBits() == 64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
new file mode 100644
index 0000000000000..dd7335362c6bd
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
@@ -0,0 +1,136 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfh -target-abi ilp32f \
+; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IZFH %s
+
+define half @callee_half_in_regs(half %x) nounwind {
+ ; RV32I-LABEL: name: callee_half_in_regs
+ ; RV32I: bb.1 (%ir-block.0):
+ ; RV32I-NEXT: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32IZFH-LABEL: name: callee_half_in_regs
+ ; RV32IZFH: bb.1 (%ir-block.0):
+ ; RV32IZFH-NEXT: liveins: $f10_h
+ ; RV32IZFH-NEXT: {{ $}}
+ ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
+ ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
+ ret half %x
+}
+
+define half @callee_half_mixed_with_int(i32 %x0, half %x) nounwind {
+ ; RV32I-LABEL: name: callee_half_mixed_with_int
+ ; RV32I: bb.1 (%ir-block.0):
+ ; RV32I-NEXT: liveins: $x10, $x11
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32IZFH-LABEL: name: callee_half_mixed_with_int
+ ; RV32IZFH: bb.1 (%ir-block.0):
+ ; RV32IZFH-NEXT: liveins: $x10, $f10_h
+ ; RV32IZFH-NEXT: {{ $}}
+ ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: $f10_h = COPY [[COPY1]](s16)
+ ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
+ ret half %x
+}
+
+define half @callee_half_return_stack1(i32 %v1, i32 %v2, i32 %v3, i32 %v4, i32 %v5, i32 %v6, i32 %v7, i32 %v8, half %x) nounwind {
+ ; RV32I-LABEL: name: callee_half_return_stack1
+ ; RV32I: bb.1 (%ir-block.0):
+ ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32I-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32I-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32I-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32I-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32I-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32I-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16)
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32IZFH-LABEL: name: callee_half_return_stack1
+ ; RV32IZFH: bb.1 (%ir-block.0):
+ ; RV32IZFH-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_h
+ ; RV32IZFH-NEXT: {{ $}}
+ ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32IZFH-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32IZFH-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32IZFH-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32IZFH-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32IZFH-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32IZFH-NEXT: [[COPY8:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: $f10_h = COPY [[COPY8]](s16)
+ ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
+ ret half %x
+}
+
+define half @callee_half_return_stack2(half %v1, half %v2, half %v3, half %v4, half %v5, half %v6, half %v7, half %v8, half %x) nounwind {
+ ; RV32I-LABEL: name: callee_half_return_stack2
+ ; RV32I: bb.1 (%ir-block.0):
+ ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32I-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
+ ; RV32I-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32I-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32)
+ ; RV32I-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32I-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32)
+ ; RV32I-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32I-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32)
+ ; RV32I-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32I-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[COPY7]](s32)
+ ; RV32I-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32I-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16)
+ ; RV32I-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC8]](s16)
+ ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32IZFH-LABEL: name: callee_half_return_stack2
+ ; RV32IZFH: bb.1 (%ir-block.0):
+ ; RV32IZFH-NEXT: liveins: $x10, $f10_h, $f11_h, $f12_h, $f13_h, $f14_h, $f15_h, $f16_h, $f17_h
+ ; RV32IZFH-NEXT: {{ $}}
+ ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+ ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f12_h
+ ; RV32IZFH-NEXT: [[COPY3:%[0-9]+]]:_(s16) = COPY $f13_h
+ ; RV32IZFH-NEXT: [[COPY4:%[0-9]+]]:_(s16) = COPY $f14_h
+ ; RV32IZFH-NEXT: [[COPY5:%[0-9]+]]:_(s16) = COPY $f15_h
+ ; RV32IZFH-NEXT: [[COPY6:%[0-9]+]]:_(s16) = COPY $f16_h
+ ; RV32IZFH-NEXT: [[COPY7:%[0-9]+]]:_(s16) = COPY $f17_h
+ ; RV32IZFH-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32IZFH-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s32)
+ ; RV32IZFH-NEXT: $f10_h = COPY [[TRUNC]](s16)
+ ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
+ ret half %x
+}
>From b470fb61e5951eaabf999961e17a1be1c19c9f21 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Fri, 7 Jun 2024 23:52:10 +0800
Subject: [PATCH 2/3] [GISel][RISCV] Add caller tests. NFC.
---
.../irtranslator/calling-conv-half.ll | 215 +++++++++++++++++-
1 file changed, 211 insertions(+), 4 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
index dd7335362c6bd..28e812fd62ebc 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
@@ -1,9 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator \
-; RUN: -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv32 -mattr=+zfh -target-abi ilp32f \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zfh -global-isel -stop-after=irtranslator < %s \
; RUN: | FileCheck -check-prefix=RV32IZFH %s
define half @callee_half_in_regs(half %x) nounwind {
@@ -27,6 +25,40 @@ define half @callee_half_in_regs(half %x) nounwind {
ret half %x
}
+define half @caller_half_in_regs(half %x) nounwind {
+ ; RV32I-LABEL: name: caller_half_in_regs
+ ; RV32I: bb.1 (%ir-block.0):
+ ; RV32I-NEXT: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10
+ ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32IZFH-LABEL: name: caller_half_in_regs
+ ; RV32IZFH: bb.1 (%ir-block.0):
+ ; RV32IZFH-NEXT: liveins: $f10_h
+ ; RV32IZFH-NEXT: {{ $}}
+ ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
+ ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_h, implicit-def $f10_h
+ ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: $f10_h = COPY [[COPY1]](s16)
+ ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
+ %y = call half @caller_half_in_regs(half %x)
+ ret half %y
+}
+
define half @callee_half_mixed_with_int(i32 %x0, half %x) nounwind {
; RV32I-LABEL: name: callee_half_mixed_with_int
; RV32I: bb.1 (%ir-block.0):
@@ -50,6 +82,44 @@ define half @callee_half_mixed_with_int(i32 %x0, half %x) nounwind {
ret half %x
}
+define half @caller_half_mixed_with_int(half %x, i32 %x0) nounwind {
+ ; RV32I-LABEL: name: caller_half_mixed_with_int
+ ; RV32I: bb.1 (%ir-block.0):
+ ; RV32I-NEXT: liveins: $x10, $x11
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32I-NEXT: $x10 = COPY [[COPY1]](s32)
+ ; RV32I-NEXT: $x11 = COPY [[ANYEXT]](s32)
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32IZFH-LABEL: name: caller_half_mixed_with_int
+ ; RV32IZFH: bb.1 (%ir-block.0):
+ ; RV32IZFH-NEXT: liveins: $x10, $f10_h
+ ; RV32IZFH-NEXT: {{ $}}
+ ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IZFH-NEXT: $x10 = COPY [[COPY1]](s32)
+ ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
+ ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_h, implicit-def $f10_h
+ ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: $f10_h = COPY [[COPY2]](s16)
+ ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
+ %y = call half @callee_half_mixed_with_int(i32 %x0, half %x)
+ ret half %y
+}
+
define half @callee_half_return_stack1(i32 %v1, i32 %v2, i32 %v3, i32 %v4, i32 %v5, i32 %v6, i32 %v7, i32 %v8, half %x) nounwind {
; RV32I-LABEL: name: callee_half_return_stack1
; RV32I: bb.1 (%ir-block.0):
@@ -88,6 +158,75 @@ define half @callee_half_return_stack1(i32 %v1, i32 %v2, i32 %v3, i32 %v4, i32 %
ret half %x
}
+define half @caller_half_return_stack1(i32 %v1, half %x) nounwind {
+ ; RV32I-LABEL: name: caller_half_return_stack1
+ ; RV32I: bb.1 (%ir-block.0):
+ ; RV32I-NEXT: liveins: $x10, $x11
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+ ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; RV32I-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
+ ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C7]](s32)
+ ; RV32I-NEXT: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
+ ; RV32I-NEXT: $x10 = COPY [[C]](s32)
+ ; RV32I-NEXT: $x11 = COPY [[C1]](s32)
+ ; RV32I-NEXT: $x12 = COPY [[C2]](s32)
+ ; RV32I-NEXT: $x13 = COPY [[COPY]](s32)
+ ; RV32I-NEXT: $x14 = COPY [[C3]](s32)
+ ; RV32I-NEXT: $x15 = COPY [[C4]](s32)
+ ; RV32I-NEXT: $x16 = COPY [[C5]](s32)
+ ; RV32I-NEXT: $x17 = COPY [[C6]](s32)
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
+ ; RV32I-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
+ ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32IZFH-LABEL: name: caller_half_return_stack1
+ ; RV32IZFH: bb.1 (%ir-block.0):
+ ; RV32IZFH-NEXT: liveins: $x10, $f10_h
+ ; RV32IZFH-NEXT: {{ $}}
+ ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; RV32IZFH-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; RV32IZFH-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; RV32IZFH-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; RV32IZFH-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+ ; RV32IZFH-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; RV32IZFH-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IZFH-NEXT: $x10 = COPY [[C]](s32)
+ ; RV32IZFH-NEXT: $x11 = COPY [[C1]](s32)
+ ; RV32IZFH-NEXT: $x12 = COPY [[C2]](s32)
+ ; RV32IZFH-NEXT: $x13 = COPY [[COPY]](s32)
+ ; RV32IZFH-NEXT: $x14 = COPY [[C3]](s32)
+ ; RV32IZFH-NEXT: $x15 = COPY [[C4]](s32)
+ ; RV32IZFH-NEXT: $x16 = COPY [[C5]](s32)
+ ; RV32IZFH-NEXT: $x17 = COPY [[C6]](s32)
+ ; RV32IZFH-NEXT: $f10_h = COPY [[COPY1]](s16)
+ ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_h, implicit-def $f10_h
+ ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: $f10_h = COPY [[COPY2]](s16)
+ ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
+ %y = call half @callee_half_return_stack1(i32 0, i32 1, i32 2, i32 %v1, i32 5, i32 6, i32 7, i32 8, half %x)
+ ret half %y
+}
+
define half @callee_half_return_stack2(half %v1, half %v2, half %v3, half %v4, half %v5, half %v6, half %v7, half %v8, half %x) nounwind {
; RV32I-LABEL: name: callee_half_return_stack2
; RV32I: bb.1 (%ir-block.0):
@@ -134,3 +273,71 @@ define half @callee_half_return_stack2(half %v1, half %v2, half %v3, half %v4, h
; RV32IZFH-NEXT: PseudoRET implicit $f10_h
ret half %x
}
+
+define half @caller_half_return_stack2(half %x, half %y) nounwind {
+ ; RV32I-LABEL: name: caller_half_return_stack2
+ ; RV32I: bb.1 (%ir-block.0):
+ ; RV32I-NEXT: liveins: $x10, $x11
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; RV32I-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+ ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; RV32I-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
+ ; RV32I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
+ ; RV32I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
+ ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s32)
+ ; RV32I-NEXT: G_STORE [[ANYEXT8]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
+ ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
+ ; RV32I-NEXT: $x11 = COPY [[ANYEXT1]](s32)
+ ; RV32I-NEXT: $x12 = COPY [[ANYEXT2]](s32)
+ ; RV32I-NEXT: $x13 = COPY [[ANYEXT3]](s32)
+ ; RV32I-NEXT: $x14 = COPY [[ANYEXT4]](s32)
+ ; RV32I-NEXT: $x15 = COPY [[ANYEXT5]](s32)
+ ; RV32I-NEXT: $x16 = COPY [[ANYEXT6]](s32)
+ ; RV32I-NEXT: $x17 = COPY [[ANYEXT7]](s32)
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
+ ; RV32I-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
+ ; RV32I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
+ ; RV32I-NEXT: $x10 = COPY [[ANYEXT9]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32IZFH-LABEL: name: caller_half_return_stack2
+ ; RV32IZFH: bb.1 (%ir-block.0):
+ ; RV32IZFH-NEXT: liveins: $f10_h, $f11_h
+ ; RV32IZFH-NEXT: {{ $}}
+ ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+ ; RV32IZFH-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+ ; RV32IZFH-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
+ ; RV32IZFH-NEXT: $f11_h = COPY [[C]](s16)
+ ; RV32IZFH-NEXT: $f12_h = COPY [[COPY]](s16)
+ ; RV32IZFH-NEXT: $f13_h = COPY [[C1]](s16)
+ ; RV32IZFH-NEXT: $f14_h = COPY [[COPY]](s16)
+ ; RV32IZFH-NEXT: $f15_h = COPY [[COPY1]](s16)
+ ; RV32IZFH-NEXT: $f16_h = COPY [[COPY1]](s16)
+ ; RV32IZFH-NEXT: $f17_h = COPY [[COPY1]](s16)
+ ; RV32IZFH-NEXT: $x10 = COPY [[COPY]](s16)
+ ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_h, implicit $f11_h, implicit $f12_h, implicit $f13_h, implicit $f14_h, implicit $f15_h, implicit $f16_h, implicit $f17_h, implicit $x10, implicit-def $f10_h
+ ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; RV32IZFH-NEXT: $f10_h = COPY [[COPY2]](s16)
+ ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
+ %z = call half @callee_half_return_stack2(half %x, half 1.0, half %x, half 3.0, half %x, half %y, half %y, half %y, half %x)
+ ret half %z
+}
>From 3b92617c4edc603b6632eb7c071f6218042d797a Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Sat, 8 Jun 2024 00:26:57 +0800
Subject: [PATCH 3/3] [GISel][RISCV] Add +f tests. NFC.
---
.../irtranslator/calling-conv-half.ll | 173 ++++++++++++++++++
1 file changed, 173 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
index 28e812fd62ebc..0a0828e51893f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+f -global-isel -stop-after=irtranslator < %s \
+; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv32 -mattr=+zfh -global-isel -stop-after=irtranslator < %s \
; RUN: | FileCheck -check-prefix=RV32IZFH %s
@@ -15,6 +17,16 @@ define half @callee_half_in_regs(half %x) nounwind {
; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
+ ; RV32IF-LABEL: name: callee_half_in_regs
+ ; RV32IF: bb.1 (%ir-block.0):
+ ; RV32IF-NEXT: liveins: $f10_f
+ ; RV32IF-NEXT: {{ $}}
+ ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
+ ; RV32IF-NEXT: PseudoRET implicit $f10_f
+ ;
; RV32IZFH-LABEL: name: callee_half_in_regs
; RV32IZFH: bb.1 (%ir-block.0):
; RV32IZFH-NEXT: liveins: $f10_h
@@ -43,6 +55,23 @@ define half @caller_half_in_regs(half %x) nounwind {
; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
+ ; RV32IF-LABEL: name: caller_half_in_regs
+ ; RV32IF: bb.1 (%ir-block.0):
+ ; RV32IF-NEXT: liveins: $f10_f
+ ; RV32IF-NEXT: {{ $}}
+ ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
+ ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit-def $f10_f
+ ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT1]](s32)
+ ; RV32IF-NEXT: PseudoRET implicit $f10_f
+ ;
; RV32IZFH-LABEL: name: caller_half_in_regs
; RV32IZFH: bb.1 (%ir-block.0):
; RV32IZFH-NEXT: liveins: $f10_h
@@ -71,6 +100,17 @@ define half @callee_half_mixed_with_int(i32 %x0, half %x) nounwind {
; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
+ ; RV32IF-LABEL: name: callee_half_mixed_with_int
+ ; RV32IF: bb.1 (%ir-block.0):
+ ; RV32IF-NEXT: liveins: $x10, $f10_f
+ ; RV32IF-NEXT: {{ $}}
+ ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
+ ; RV32IF-NEXT: PseudoRET implicit $f10_f
+ ;
; RV32IZFH-LABEL: name: callee_half_mixed_with_int
; RV32IZFH: bb.1 (%ir-block.0):
; RV32IZFH-NEXT: liveins: $x10, $f10_h
@@ -102,6 +142,25 @@ define half @caller_half_mixed_with_int(half %x, i32 %x0) nounwind {
; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
+ ; RV32IF-LABEL: name: caller_half_mixed_with_int
+ ; RV32IF: bb.1 (%ir-block.0):
+ ; RV32IF-NEXT: liveins: $x10, $f10_f
+ ; RV32IF-NEXT: {{ $}}
+ ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32IF-NEXT: $x10 = COPY [[COPY1]](s32)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
+ ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $f10_f
+ ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT1]](s32)
+ ; RV32IF-NEXT: PseudoRET implicit $f10_f
+ ;
; RV32IZFH-LABEL: name: caller_half_mixed_with_int
; RV32IZFH: bb.1 (%ir-block.0):
; RV32IZFH-NEXT: liveins: $x10, $f10_h
@@ -140,6 +199,24 @@ define half @callee_half_return_stack1(i32 %v1, i32 %v2, i32 %v3, i32 %v4, i32 %
; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
+ ; RV32IF-LABEL: name: callee_half_return_stack1
+ ; RV32IF: bb.1 (%ir-block.0):
+ ; RV32IF-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f
+ ; RV32IF-NEXT: {{ $}}
+ ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32IF-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32IF-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32IF-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32IF-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32IF-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32IF-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s32)
+ ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
+ ; RV32IF-NEXT: PseudoRET implicit $f10_f
+ ;
; RV32IZFH-LABEL: name: callee_half_return_stack1
; RV32IZFH: bb.1 (%ir-block.0):
; RV32IZFH-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_h
@@ -195,6 +272,39 @@ define half @caller_half_return_stack1(i32 %v1, half %x) nounwind {
; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
+ ; RV32IF-LABEL: name: caller_half_return_stack1
+ ; RV32IF: bb.1 (%ir-block.0):
+ ; RV32IF-NEXT: liveins: $x10, $f10_f
+ ; RV32IF-NEXT: {{ $}}
+ ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; RV32IF-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; RV32IF-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; RV32IF-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; RV32IF-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; RV32IF-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+ ; RV32IF-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; RV32IF-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32IF-NEXT: $x10 = COPY [[C]](s32)
+ ; RV32IF-NEXT: $x11 = COPY [[C1]](s32)
+ ; RV32IF-NEXT: $x12 = COPY [[C2]](s32)
+ ; RV32IF-NEXT: $x13 = COPY [[COPY]](s32)
+ ; RV32IF-NEXT: $x14 = COPY [[C3]](s32)
+ ; RV32IF-NEXT: $x15 = COPY [[C4]](s32)
+ ; RV32IF-NEXT: $x16 = COPY [[C5]](s32)
+ ; RV32IF-NEXT: $x17 = COPY [[C6]](s32)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
+ ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $f10_f
+ ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT1]](s32)
+ ; RV32IF-NEXT: PseudoRET implicit $f10_f
+ ;
; RV32IZFH-LABEL: name: caller_half_return_stack1
; RV32IZFH: bb.1 (%ir-block.0):
; RV32IZFH-NEXT: liveins: $x10, $f10_h
@@ -255,6 +365,32 @@ define half @callee_half_return_stack2(half %v1, half %v2, half %v3, half %v4, h
; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
+ ; RV32IF-LABEL: name: callee_half_return_stack2
+ ; RV32IF: bb.1 (%ir-block.0):
+ ; RV32IF-NEXT: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV32IF-NEXT: {{ $}}
+ ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
+ ; RV32IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; RV32IF-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
+ ; RV32IF-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
+ ; RV32IF-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
+ ; RV32IF-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32)
+ ; RV32IF-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
+ ; RV32IF-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32)
+ ; RV32IF-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
+ ; RV32IF-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32)
+ ; RV32IF-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
+ ; RV32IF-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[COPY7]](s32)
+ ; RV32IF-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32IF-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s32)
+ ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC8]](s16)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
+ ; RV32IF-NEXT: PseudoRET implicit $f10_f
+ ;
; RV32IZFH-LABEL: name: callee_half_return_stack2
; RV32IZFH: bb.1 (%ir-block.0):
; RV32IZFH-NEXT: liveins: $x10, $f10_h, $f11_h, $f12_h, $f13_h, $f14_h, $f15_h, $f16_h, $f17_h
@@ -315,6 +451,43 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
; RV32I-NEXT: $x10 = COPY [[ANYEXT9]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
+ ; RV32IF-LABEL: name: caller_half_return_stack2
+ ; RV32IF: bb.1 (%ir-block.0):
+ ; RV32IF-NEXT: liveins: $f10_f, $f11_f
+ ; RV32IF-NEXT: {{ $}}
+ ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; RV32IF-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+ ; RV32IF-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
+ ; RV32IF-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32IF-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
+ ; RV32IF-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32IF-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32IF-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32IF-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
+ ; RV32IF-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
+ ; RV32IF-NEXT: $f11_f = COPY [[ANYEXT1]](s32)
+ ; RV32IF-NEXT: $f12_f = COPY [[ANYEXT2]](s32)
+ ; RV32IF-NEXT: $f13_f = COPY [[ANYEXT3]](s32)
+ ; RV32IF-NEXT: $f14_f = COPY [[ANYEXT4]](s32)
+ ; RV32IF-NEXT: $f15_f = COPY [[ANYEXT5]](s32)
+ ; RV32IF-NEXT: $f16_f = COPY [[ANYEXT6]](s32)
+ ; RV32IF-NEXT: $f17_f = COPY [[ANYEXT7]](s32)
+ ; RV32IF-NEXT: $x10 = COPY [[ANYEXT8]](s32)
+ ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $f10_f
+ ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; RV32IF-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
+ ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT9]](s32)
+ ; RV32IF-NEXT: PseudoRET implicit $f10_f
+ ;
; RV32IZFH-LABEL: name: caller_half_return_stack2
; RV32IZFH: bb.1 (%ir-block.0):
; RV32IZFH-NEXT: liveins: $f10_h, $f11_h
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