[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 7 07:59:28 PDT 2024
================
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+ NoSchedModel,
+ !listconcat(RVA22S64Features,
+ [FeatureStdExtV,
+ FeatureStdExtSvnapot,
+ FeatureStdExtZbc,
+ FeatureStdExtZbkc,
+ FeatureStdExtZfh,
+ FeatureStdExtZicond,
+ FeatureStdExtZmmul,
+ FeatureStdExtZvfh,
+ FeatureStdExtZvfhmin,
+ FeatureStdExtZvl32b,
+ FeatureStdExtZvl64b,
+ FeatureStdExtZvl128b,
+ FeatureStdExtZvl256b])>;
----------------
preames wrote:
Zvl256 implies Zvl32 through Zvl128, so those don't need to be explicitly repeated.
Per the docs, the actual execution width is 128 bit so we could add [TuneDLenFactor2] to the tuning list.
https://github.com/llvm/llvm-project/pull/94564
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