[llvm] [SDISel][Builder] Fix the instantiation of <1 x bfloat|half> (PR #94591)

[Quentin Colombet via llvm-commits]

qcolombet wrote:

I've pushed an additional commit to fix the arm test that was failing in CI.
This test was lucky with the old (broken) way of lowering half and was getting a constant folding that we don't get anymore.

For this particular case the input SDNodes are:
```
          t2: v1f16 = BUILD_VECTOR ConstantFP:f16<APFloat(0)>
        t4: v1f16 = insert_vector_elt t2, ConstantFP:f16<APFloat(0)>, Constant:i32<0>
      t5: f16 = bitcast t4
    t6: f32 = fp_extend t5
```

And just before selection we end up with:
```
 t11: f32 = fp16_to_fp Constant:i32<0>
```

I.e., a very silly missed folding.

Whereas the previous code would generate right of SDBuilder:
```
  t7: ch = CopyToReg t0, Register:f32 %0, ConstantFP:f32<0.000000e+00>
```

I have a fix, but I'll create a separate PR.

https://github.com/llvm/llvm-project/pull/94591