[llvm] [AMDGPU][WIP] Optimize SGPR spills (PR #93668)

[Vikash Gupta via llvm-commits]

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@@ -362,10 +362,12 @@
 ; GCN-O1-NEXT:        Machine Optimization Remark Emitter
 ; GCN-O1-NEXT:        Greedy Register Allocator
 ; GCN-O1-NEXT:        Virtual Register Rewriter
+; GCN-O1-NEXT:        Stack Slot Coloring
 ; GCN-O1-NEXT:        SI lower SGPR spill instructions
 ; GCN-O1-NEXT:        Virtual Register Map
 ; GCN-O1-NEXT:        Live Register Matrix
 ; GCN-O1-NEXT:        SI Pre-allocate WWM Registers
+; GCN-O1-NEXT:        Live Stack Slot Analysis
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vg0204 wrote:

Need to look into it, but I cannot say how much changes might it take. Also, as the same LiveStack(LS) would be propagated into RA pass later for entring additional entries, RA might have some side effects while working on presereved LS. Considering all this, this updates might take big significant effort, followed by rigourous tests, so nothing else breaks.

https://github.com/llvm/llvm-project/pull/93668