[llvm] [AMDGPU][LIT] Added a MIR LIT showing the SGPR spills (PR #94584)

[Matt Arsenault via llvm-commits]

================
@@ -8,44 +8,53 @@
 # In the remaining 2 test cases mentioned in just above 2 lines, the stack slot indices is shared among the spill stack objects of
 # unequal size, with spill slot having the size of the largest of the stack objects sharing the common stack indices.
 
---- |
-  define void @stack-slot-share-equal-sized-spills(ptr addrspace(1) nocapture readnone %arg, ptr addrspace(1) noalias %arg1) {
-  bb:
-    %tmp = load i32, ptr addrspace(1) null, align 4
-    call void @func(i32 undef)
-    call void @func(i32 %tmp)
-    unreachable
-  }
-
-  define void @stack-slot-share-unequal-sized-spills-with-large-spill-first(ptr addrspace(1) nocapture readnone %arg, ptr addrspace(1) noalias %arg1) {
-  bb:
-    %tmp = load i32, ptr addrspace(1) null, align 4
-    call void @func(i32 undef)
-    call void @func(i32 %tmp)
-    unreachable
-  }
-
-  define void @stack-slot-share-unequal-sized-spills-with-small-spill-first(ptr addrspace(1) nocapture readnone %arg, ptr addrspace(1) noalias %arg1) {
-  bb:
-    %tmp = load i32, ptr addrspace(1) null, align 4
-    call void @func(i32 undef)
-    call void @func(i32 %tmp)
-    unreachable
-  }
-
-  declare void @func(i32)
-...
-
 ---
 name:            stack-slot-share-equal-sized-spills
+alignment:       1
 tracksRegLiveness: true
+tracksDebugUserValues: true
+registers:
+  - { id: 0, class: sreg_32_xm0_xexec }
+  - { id: 1, class: sreg_64_xexec }
+  - { id: 2, class: vreg_64 }
+  - { id: 3, class: vgpr_32, preferred-register: '$vgpr0' }
+  - { id: 4, class: sreg_64 }
+  - { id: 5, class: sreg_32_xm0_xexec }
+  - { id: 6, class: sreg_64_xexec }
+  - { id: 7, class: sreg_64 }
+  - { id: 8, class: sreg_64 }
+  - { id: 9, class: sreg_64 }
 frameInfo:
+  maxAlignment:    4
   adjustsStack:    true
   hasCalls:        true
+stack:
+  - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
+  - { id: 1, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
+  - { id: 2, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
+  - { id: 3, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
+  - { id: 4, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
 machineFunctionInfo:
-  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
-  frameOffsetReg: $sgpr32
-  stackPtrOffsetReg: $sgpr32
+  maxKernArgAlign: 1
+  hasSpilledSGPRs: true
+  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
+  frameOffsetReg:  '$sgpr32'
+  stackPtrOffsetReg: '$sgpr32'
+  argumentInfo:
+    privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
+    dispatchPtr:     { reg: '$sgpr4_sgpr5' }
+    queuePtr:        { reg: '$sgpr6_sgpr7' }
+    dispatchID:      { reg: '$sgpr10_sgpr11' }
+    workGroupIDX:    { reg: '$sgpr12' }
+    workGroupIDY:    { reg: '$sgpr13' }
+    workGroupIDZ:    { reg: '$sgpr14' }
+    LDSKernelId:     { reg: '$sgpr15' }
+    implicitArgPtr:  { reg: '$sgpr8_sgpr9' }
+    workItemIDX:     { reg: '$vgpr31', mask: 1023 }
+    workItemIDY:     { reg: '$vgpr31', mask: 1047552 }
+    workItemIDZ:     { reg: '$vgpr31', mask: 1072693248 }
----------------
arsenm wrote:

Remove this 

https://github.com/llvm/llvm-project/pull/94584