[llvm] [AMDGPU][WIP] Optimize SGPR spills (PR #93668)

[Vikash Gupta via llvm-commits]

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@@ -362,10 +362,12 @@
 ; GCN-O1-NEXT:        Machine Optimization Remark Emitter
 ; GCN-O1-NEXT:        Greedy Register Allocator
 ; GCN-O1-NEXT:        Virtual Register Rewriter
+; GCN-O1-NEXT:        Stack Slot Coloring
 ; GCN-O1-NEXT:        SI lower SGPR spill instructions
 ; GCN-O1-NEXT:        Virtual Register Map
 ; GCN-O1-NEXT:        Live Register Matrix
 ; GCN-O1-NEXT:        SI Pre-allocate WWM Registers
+; GCN-O1-NEXT:        Live Stack Slot Analysis
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vg0204 wrote:

I tried this & found that as StackSlotColoring pass is not currently updating LiveStacks(LS) analysis, eventhough modifying the stack slots usage (as before it is being invoked only after complete RA when all spills happened just before PEI, so LS not needed anymore), so LS results are invalidated rather preserved. But, now LS is being needed by RA (for remaining register class) later, so LS analysis appears later as being re-calculated. 

https://github.com/llvm/llvm-project/pull/93668