[llvm] [RISCV] Support Inline ASM for the bf16 type. (PR #80118)

[Chuan-Yue Yuan via llvm-commits]

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@@ -479,6 +479,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     // FIXME: Need to promote bf16 FCOPYSIGN to f32, but the
     // DAGCombiner::visitFP_ROUND probably needs improvements first.
     setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Expand);
+
+    // To fold (bf16 bitcast (copyfromreg f16)) -> (copyfromreg bf16), we have
+    // to legalize the f16 CopyFromReg for avoiding SoftPromoteHalf.
+    setOperationAction(ISD::CopyFromReg, MVT::f16, Legal);
+    // Fold the (bf16 bitcast (copyfromreg f16)) -> (copyfromreg bf16).
+    setTargetDAGCombine(ISD::BITCAST);
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circYuan wrote:

If I don't combine the bitcast this time, the new test I added would be fail since RISCV doesn't have the instruction for selecting the `bf16 bitcast fp16`. In the IR level, it even doesn't allow the bitcast between fp16 <--> bf16.

https://github.com/llvm/llvm-project/pull/80118