[llvm] [RISCV] Support Inline ASM for the bf16 type. (PR #80118)

[Matt Arsenault via llvm-commits]

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@@ -17088,10 +17094,30 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
     }
   }
   case ISD::BITCAST: {
-    assert(Subtarget.useRVVForFixedLengthVectors());
+    assert(Subtarget.useRVVForFixedLengthVectors() ||
+           Subtarget.hasStdExtZfbfmin());
     SDValue N0 = N->getOperand(0);
     EVT VT = N->getValueType(0);
     EVT SrcVT = N0.getValueType();
+
+    // Fold the (bf16 bitcast (copyfromreg f16)) -> (copyfromreg bf16).
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arsenm wrote:

This should probably be rewritten as a generic combine for any pairs where isTypeLegalForClass is true in both registers 

https://github.com/llvm/llvm-project/pull/80118