[llvm] [AArch64][GISel] Assign registers into FPR if they feed into FP instructions indirectly via PHI (PR #94618)

[Matt Arsenault via llvm-commits]

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@@ -117,6 +117,7 @@ class MachineInstr
     NoConvergent = 1 << 17,  // Call does not require convergence guarantees.
     NonNeg = 1 << 18,        // The operand is non-negative.
     Disjoint = 1 << 19,      // Each bit is zero in at least one of the inputs.
+    DefinesFP = 1 << 20,     // Defines floating-point value
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arsenm wrote:

This does not belong as an instruction flag 

https://github.com/llvm/llvm-project/pull/94618