[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)

via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 5 21:13:59 PDT 2024


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Shao-Ce SUN (sunshaoce)

<details>
<summary>Changes</summary>

Spacemit-k1 is a new 8-core CPU that supports RVV 1.0, and it is now integrated into the BPi-F3 development board. 

Through [ruapo](https://github.com/nihui/ruapu) detection, this is the march information of Spacemit-K1:
```
i
m
a
f
d
c
v
zba
zbb
zbc
zbs
zbkb
zbkc
zfh
zfhmin
zicond
zicsr
zifencei
zmmul
zvfh
zvfhmin
zvl32b
zvl64b
zvl128b
zvl256b
```


BPi-F3 Datasheet: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet
Spacemit-K1 Datasheet: https://developer.spacemit.com/#/documentation?token=DBd4wvqoqi2fiqkiERTcbEDknBh

---
Full diff: https://github.com/llvm/llvm-project/pull/94564.diff


3 Files Affected:

- (modified) clang/test/Driver/riscv-cpus.c (+12) 
- (modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2) 
- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+29) 


``````````diff
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck -check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v" "-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature" "+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc" "-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature" "+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature" "+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
 // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtHFusion,
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+                                   NoSchedModel,
+                                   [Feature64Bit,
+                                    FeatureStdExtI,
+                                    FeatureStdExtM,
+                                    FeatureStdExtA,
+                                    FeatureStdExtF,
+                                    FeatureStdExtD,
+                                    FeatureStdExtC,
+                                    FeatureStdExtV,
+                                    FeatureStdExtZba,
+                                    FeatureStdExtZbb,
+                                    FeatureStdExtZbc,
+                                    FeatureStdExtZbs,
+                                    FeatureStdExtZbkb,
+                                    FeatureStdExtZbkc,
+                                    FeatureStdExtZfh,
+                                    FeatureStdExtZfhmin,
+                                    FeatureStdExtZicond,
+                                    FeatureStdExtZicsr,
+                                    FeatureStdExtZifencei,
+                                    FeatureStdExtZmmul,
+                                    FeatureStdExtZvfh,
+                                    FeatureStdExtZvfhmin,
+                                    FeatureStdExtZvl32b,
+                                    FeatureStdExtZvl64b,
+                                    FeatureStdExtZvl128b,
+                                    FeatureStdExtZvl256b]>;

``````````

</details>


https://github.com/llvm/llvm-project/pull/94564


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