[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[via llvm-commits]

================
@@ -113,7 +109,51 @@ static void appendCodeTemplates(const LLVMState &State,
   }
   case ExecutionMode::SERIAL_VIA_MEMORY_INSTR: {
     // Select back-to-back memory instruction.
-    // TODO: Implement me.
+
----------------
AnastasiyaChernikova wrote:

This part of code is necessary to implemented strategy for load operation in RISCV.
Example with LD instruction without this part of code:
```
mode:            latency
key:
  instructions:
    - 'LD X12 X10 i_0x0'
    - 'SLL X17 X12 X28'
  config:          ''
  register_initial_values:
    - 'X28=0x0'
```
And with this code:
```
mode:            latency
key:
  instructions:
    - 'LD X10 X10 i_0x0'
  config:          ''
  register_initial_values: []
```
This test from latency-by-load.s

https://github.com/llvm/llvm-project/pull/89047