[llvm] [RISCV] Add groupid/bitmask for RISC-V extension (PR #94440)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 5 01:33:43 PDT 2024
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/94440
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.
This patch defines the groupid/bitmask in RISCVFeatures.td and generates the corresponding table in RISCVTargetParserDef.inc.
The groupid/bitmask of extensions provides an abstraction layer between the compiler and runtime functions.
>From 0d4af6e2f351b7e4e94d9fabbcee6ad49d6647a2 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.
This patch defines the groupid/bitmask in RISCVFeatures.td and generates the corresponding table in RISCVTargetParserDef.inc.
The groupid/bitmask of extensions provides an abstraction layer between the compiler and runtime functions.
---
.../llvm/TargetParser/RISCVTargetParser.h | 8 ++
llvm/lib/Target/RISCV/RISCVFeatures.td | 105 ++++++++++++++++++
llvm/lib/TargetParser/RISCVTargetParser.cpp | 32 ++++++
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 39 +++++++
4 files changed, 184 insertions(+)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 5b1494efe7bdc..24755dcfec52a 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,6 +24,14 @@ class Triple;
namespace RISCV {
+namespace RISCVExtensionBitmaskTable {
+struct RISCVExtensionBitmask {
+ const char *Name;
+ unsigned GroupID;
+ unsigned long long Bitmask;
+};
+} // namespace RISCVExtensionBitmaskTable
+
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9bf06850483d8..bfaa7b1a1b99b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,6 +37,13 @@ class RISCVExtension<string name, int major, int minor, string desc,
bit Experimental = false;
}
+// TODO: Maybe integrate into RISCVExtension class
+class RISCVExtensionBitmask<string name, bits<3> groupID, int bitmaskShift> {
+ string Name = name;
+ bits<3> GroupID = groupID;
+ bits<64> Bitmask = !shl(1, bitmaskShift);
+}
+
// Version of RISCVExtension to be used for Experimental extensions. This
// sets the Experimental flag and prepends experimental- to the -mattr name.
class RISCVExperimentalExtension<string name, int major, int minor, string desc,
@@ -53,18 +60,22 @@ class RISCVExperimentalExtension<string name, int major, int minor, string desc,
def FeatureStdExtI
: RISCVExtension<"i", 2, 1,
"'I' (Base Integer Instruction Set)">;
+def : RISCVExtensionBitmask<"i", 0, 0>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
"Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
+def : RISCVExtensionBitmask<"e", 0, 1>;
def FeatureStdExtZic64b
: RISCVExtension<"zic64b", 1, 0,
"'Zic64b' (Cache Block Size Is 64 Bytes)">;
+def : RISCVExtensionBitmask<"zic64b", 0, 2>;
def FeatureStdExtZicbom
: RISCVExtension<"zicbom", 1, 0,
"'Zicbom' (Cache-Block Management Instructions)">;
+def : RISCVExtensionBitmask<"zicbom", 0, 3>;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -72,6 +83,7 @@ def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
def FeatureStdExtZicbop
: RISCVExtension<"zicbop", 1, 0,
"'Zicbop' (Cache-Block Prefetch Instructions)">;
+def : RISCVExtensionBitmask<"zicbop", 0, 4>;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
@@ -79,6 +91,7 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
"'Zicboz' (Cache-Block Zero Instructions)">;
+def : RISCVExtensionBitmask<"zicboz", 0, 5>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
@@ -86,22 +99,27 @@ def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
def FeatureStdExtZiccamoa
: RISCVExtension<"ziccamoa", 1, 0,
"'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+def : RISCVExtensionBitmask<"ziccamoa", 0, 6>;
def FeatureStdExtZiccif
: RISCVExtension<"ziccif", 1, 0,
"'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
+def : RISCVExtensionBitmask<"ziccif", 0, 7>;
def FeatureStdExtZicclsm
: RISCVExtension<"zicclsm", 1, 0,
"'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
+def : RISCVExtensionBitmask<"zicclsm", 0, 8>;
def FeatureStdExtZiccrse
: RISCVExtension<"ziccrse", 1, 0,
"'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
+def : RISCVExtensionBitmask<"ziccrse", 0, 9>;
def FeatureStdExtZicsr
: RISCVExtension<"zicsr", 2, 0,
"'zicsr' (CSRs)">;
+def : RISCVExtensionBitmask<"zicsr", 0, 10>;
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
@@ -110,10 +128,12 @@ def FeatureStdExtZicntr
: RISCVExtension<"zicntr", 2, 0,
"'Zicntr' (Base Counters and Timers)",
[FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"zicntr", 0, 11>;
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
"'Zicond' (Integer Conditional Operations)">;
+def : RISCVExtensionBitmask<"zicond", 0, 12>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
@@ -121,6 +141,7 @@ def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
def FeatureStdExtZifencei
: RISCVExtension<"zifencei", 2, 0,
"'Zifencei' (fence.i)">;
+def : RISCVExtensionBitmask<"zifencei", 0, 13>;
def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
@@ -128,6 +149,7 @@ def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
def FeatureStdExtZihintpause
: RISCVExtension<"zihintpause", 2, 0,
"'Zihintpause' (Pause Hint)">;
+def : RISCVExtensionBitmask<"zihintpause", 0, 14>;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
@@ -135,6 +157,7 @@ def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
"'Zihintntl' (Non-Temporal Locality Hints)">;
+def : RISCVExtensionBitmask<"zihintntl", 0, 15>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -143,9 +166,11 @@ def FeatureStdExtZihpm
: RISCVExtension<"zihpm", 2, 0,
"'Zihpm' (Hardware Performance Counters)",
[FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"zihpm", 0, 16>;
def FeatureStdExtZimop : RISCVExtension<"zimop", 1, 0,
"'Zimop' (May-Be-Operations)">;
+def : RISCVExtensionBitmask<"zimop", 0, 17>;
def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
@@ -154,6 +179,7 @@ def FeatureStdExtZicfilp
: RISCVExperimentalExtension<"zicfilp", 0, 4,
"'Zicfilp' (Landing pad)",
[FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"zicfilp", 0, 18>;
def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
AssemblerPredicate<(all_of FeatureStdExtZicfilp),
"'Zicfilp' (Landing pad)">;
@@ -164,6 +190,7 @@ def FeatureStdExtZicfiss
: RISCVExperimentalExtension<"zicfiss", 0, 4,
"'Zicfiss' (Shadow stack)",
[FeatureStdExtZicsr, FeatureStdExtZimop]>;
+def : RISCVExtensionBitmask<"zicfiss", 0, 19>;
def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
AssemblerPredicate<(all_of FeatureStdExtZicfiss),
"'Zicfiss' (Shadow stack)">;
@@ -174,6 +201,7 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
"'M' (Integer Multiplication and Division)">;
+def : RISCVExtensionBitmask<"m", 0, 20>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
@@ -181,6 +209,7 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
def FeatureStdExtZmmul
: RISCVExtension<"zmmul", 1, 0,
"'Zmmul' (Integer Multiplication)">;
+def : RISCVExtensionBitmask<"zmmul", 0, 21>;
def HasStdExtMOrZmmul
: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
@@ -193,6 +222,7 @@ def HasStdExtMOrZmmul
def FeatureStdExtA
: RISCVExtension<"a", 2, 1,
"'A' (Atomic Instructions)">;
+def : RISCVExtensionBitmask<"a", 0, 22>;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
@@ -200,6 +230,7 @@ def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
def FeatureStdExtZtso
: RISCVExperimentalExtension<"ztso", 0, 1,
"'Ztso' (Memory Model - Total Store Order)">;
+def : RISCVExtensionBitmask<"ztso", 0, 23>;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
@@ -207,13 +238,16 @@ def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0,
"'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
+def : RISCVExtensionBitmask<"za64rs", 0, 24>;
def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
"'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
+def : RISCVExtensionBitmask<"za128rs", 0, 25>;
def FeatureStdExtZaamo
: RISCVExtension<"zaamo", 1, 0,
"'Zaamo' (Atomic Memory Operations)">;
+def : RISCVExtensionBitmask<"zaamo", 0, 26>;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -223,6 +257,7 @@ def HasStdExtAOrZaamo
def FeatureStdExtZabha
: RISCVExtension<"zabha", 1, 0,
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
+def : RISCVExtensionBitmask<"zabha", 0, 27>;
def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
AssemblerPredicate<(all_of FeatureStdExtZabha),
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
@@ -230,6 +265,7 @@ def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
def FeatureStdExtZacas
: RISCVExtension<"zacas", 1, 0,
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
+def : RISCVExtensionBitmask<"zacas", 0, 28>;
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
AssemblerPredicate<(all_of FeatureStdExtZacas),
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
@@ -238,6 +274,7 @@ def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
def FeatureStdExtZalasr
: RISCVExperimentalExtension<"zalasr", 0, 1,
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
+def : RISCVExtensionBitmask<"zalasr", 0, 29>;
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
AssemblerPredicate<(all_of FeatureStdExtZalasr),
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
@@ -245,6 +282,7 @@ def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
def FeatureStdExtZalrsc
: RISCVExtension<"zalrsc", 1, 0,
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
+def : RISCVExtensionBitmask<"zalrsc", 0, 30>;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
@@ -254,9 +292,11 @@ def HasStdExtAOrZalrsc
def FeatureStdExtZama16b
: RISCVExtension<"zama16b", 1, 0,
"'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
+def : RISCVExtensionBitmask<"zama16b", 0, 31>;
def FeatureStdExtZawrs : RISCVExtension<"zawrs", 1, 0,
"'Zawrs' (Wait on Reservation Set)">;
+def : RISCVExtensionBitmask<"zawrs", 0, 32>;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
AssemblerPredicate<(all_of FeatureStdExtZawrs),
"'Zawrs' (Wait on Reservation Set)">;
@@ -267,6 +307,7 @@ def FeatureStdExtF
: RISCVExtension<"f", 2, 2,
"'F' (Single-Precision Floating-Point)",
[FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"f", 0, 33>;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
AssemblerPredicate<(all_of FeatureStdExtF),
"'F' (Single-Precision Floating-Point)">;
@@ -275,6 +316,7 @@ def FeatureStdExtD
: RISCVExtension<"d", 2, 2,
"'D' (Double-Precision Floating-Point)",
[FeatureStdExtF]>;
+def : RISCVExtensionBitmask<"d", 0, 34>;
def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<(all_of FeatureStdExtD),
"'D' (Double-Precision Floating-Point)">;
@@ -283,6 +325,7 @@ def FeatureStdExtZfhmin
: RISCVExtension<"zfhmin", 1, 0,
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
[FeatureStdExtF]>;
+def : RISCVExtensionBitmask<"zfhmin", 0, 35>;
def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
"'Zfh' (Half-Precision Floating-Point) or "
@@ -292,6 +335,7 @@ def FeatureStdExtZfh
: RISCVExtension<"zfh", 1, 0,
"'Zfh' (Half-Precision Floating-Point)",
[FeatureStdExtZfhmin]>;
+def : RISCVExtensionBitmask<"zfh", 0, 36>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
@@ -301,6 +345,7 @@ def FeatureStdExtZfbfmin
: RISCVExperimentalExtension<"zfbfmin", 1, 0,
"'Zfbfmin' (Scalar BF16 Converts)",
[FeatureStdExtF]>;
+def : RISCVExtensionBitmask<"zfbfmin", 0, 37>;
def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
"'Zfbfmin' (Scalar BF16 Converts)">;
@@ -317,6 +362,7 @@ def FeatureStdExtZfa
: RISCVExtension<"zfa", 1, 0,
"'Zfa' (Additional Floating-Point)",
[FeatureStdExtF]>;
+def : RISCVExtensionBitmask<"zfa", 0, 38>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
AssemblerPredicate<(all_of FeatureStdExtZfa),
"'Zfa' (Additional Floating-Point)">;
@@ -325,6 +371,7 @@ def FeatureStdExtZfinx
: RISCVExtension<"zfinx", 1, 0,
"'Zfinx' (Float in Integer)",
[FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"zfinx", 0, 39>;
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
@@ -333,6 +380,7 @@ def FeatureStdExtZdinx
: RISCVExtension<"zdinx", 1, 0,
"'Zdinx' (Double in Integer)",
[FeatureStdExtZfinx]>;
+def : RISCVExtensionBitmask<"zdinx", 0, 40>;
def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
AssemblerPredicate<(all_of FeatureStdExtZdinx),
"'Zdinx' (Double in Integer)">;
@@ -341,6 +389,7 @@ def FeatureStdExtZhinxmin
: RISCVExtension<"zhinxmin", 1, 0,
"'Zhinxmin' (Half Float in Integer Minimal)",
[FeatureStdExtZfinx]>;
+def : RISCVExtensionBitmask<"zhinxmin", 0, 41>;
def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
"'Zhinx' (Half Float in Integer) or "
@@ -350,6 +399,7 @@ def FeatureStdExtZhinx
: RISCVExtension<"zhinx", 1, 0,
"'Zhinx' (Half Float in Integer)",
[FeatureStdExtZhinxmin]>;
+def : RISCVExtensionBitmask<"zhinx", 0, 42>;
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
AssemblerPredicate<(all_of FeatureStdExtZhinx),
"'Zhinx' (Half Float in Integer)">;
@@ -360,6 +410,7 @@ def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
def FeatureStdExtC
: RISCVExtension<"c", 2, 0,
"'C' (Compressed Instructions)">;
+def : RISCVExtensionBitmask<"c", 0, 43>;
def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
"'C' (Compressed Instructions)">;
@@ -375,6 +426,7 @@ def FeatureStdExtZca
: RISCVExtension<"zca", 1, 0,
"'Zca' (part of the C extension, excluding compressed "
"floating point loads/stores)">;
+def : RISCVExtensionBitmask<"zca", 0, 44>;
def HasStdExtCOrZca
: Predicate<"Subtarget->hasStdExtCOrZca()">,
@@ -387,6 +439,7 @@ def FeatureStdExtZcb
: RISCVExtension<"zcb", 1, 0,
"'Zcb' (Compressed basic bit manipulation instructions)",
[FeatureStdExtZca]>;
+def : RISCVExtensionBitmask<"zcb", 0, 45>;
def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
AssemblerPredicate<(all_of FeatureStdExtZcb),
"'Zcb' (Compressed basic bit manipulation instructions)">;
@@ -395,6 +448,7 @@ def FeatureStdExtZcd
: RISCVExtension<"zcd", 1, 0,
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
[FeatureStdExtD, FeatureStdExtZca]>;
+def : RISCVExtensionBitmask<"zcd", 0, 46>;
def HasStdExtCOrZcd
: Predicate<"Subtarget->hasStdExtCOrZcd()">,
@@ -406,11 +460,13 @@ def FeatureStdExtZcf
: RISCVExtension<"zcf", 1, 0,
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
[FeatureStdExtF, FeatureStdExtZca]>;
+def : RISCVExtensionBitmask<"zcf", 0, 47>;
def FeatureStdExtZcmp
: RISCVExtension<"zcmp", 1, 0,
"'Zcmp' (sequenced instuctions for code-size reduction)",
[FeatureStdExtZca]>;
+def : RISCVExtensionBitmask<"zcmp", 0, 48>;
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtZcmp),
"'Zcmp' (sequenced instuctions for code-size reduction)">;
@@ -419,6 +475,7 @@ def FeatureStdExtZcmt
: RISCVExtension<"zcmt", 1, 0,
"'Zcmt' (table jump instuctions for code-size reduction)",
[FeatureStdExtZca, FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"zcmt", 0, 49>;
def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
AssemblerPredicate<(all_of FeatureStdExtZcmt),
"'Zcmt' (table jump instuctions for code-size reduction)">;
@@ -427,6 +484,7 @@ def FeatureStdExtZce
: RISCVExtension<"zce", 1, 0,
"'Zce' (Compressed extensions for microcontrollers)",
[FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>;
+def : RISCVExtensionBitmask<"zce", 0, 50>;
def HasStdExtCOrZcfOrZce
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
@@ -440,6 +498,7 @@ def FeatureStdExtZcmop
: RISCVExtension<"zcmop", 1, 0,
"'Zcmop' (Compressed May-Be-Operations)",
[FeatureStdExtZca]>;
+def : RISCVExtensionBitmask<"zcmop", 0, 51>;
def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
AssemblerPredicate<(all_of FeatureStdExtZcmop),
"'Zcmop' (Compressed May-Be-Operations)">;
@@ -449,6 +508,7 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
def FeatureStdExtZba
: RISCVExtension<"zba", 1, 0,
"'Zba' (Address Generation Instructions)">;
+def : RISCVExtensionBitmask<"zba", 0, 52>;
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
AssemblerPredicate<(all_of FeatureStdExtZba),
"'Zba' (Address Generation Instructions)">;
@@ -457,6 +517,7 @@ def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
def FeatureStdExtZbb
: RISCVExtension<"zbb", 1, 0,
"'Zbb' (Basic Bit-Manipulation)">;
+def : RISCVExtensionBitmask<"zbb", 0, 53>;
def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
AssemblerPredicate<(all_of FeatureStdExtZbb),
"'Zbb' (Basic Bit-Manipulation)">;
@@ -464,6 +525,7 @@ def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
def FeatureStdExtZbc
: RISCVExtension<"zbc", 1, 0,
"'Zbc' (Carry-Less Multiplication)">;
+def : RISCVExtensionBitmask<"zbc", 0, 54>;
def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
AssemblerPredicate<(all_of FeatureStdExtZbc),
"'Zbc' (Carry-Less Multiplication)">;
@@ -471,6 +533,7 @@ def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
def FeatureStdExtZbs
: RISCVExtension<"zbs", 1, 0,
"'Zbs' (Single-Bit Instructions)">;
+def : RISCVExtensionBitmask<"zbs", 0, 55>;
def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
AssemblerPredicate<(all_of FeatureStdExtZbs),
"'Zbs' (Single-Bit Instructions)">;
@@ -480,6 +543,7 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
def FeatureStdExtZbkb
: RISCVExtension<"zbkb", 1, 0,
"'Zbkb' (Bitmanip instructions for Cryptography)">;
+def : RISCVExtensionBitmask<"zbkb", 0, 56>;
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
AssemblerPredicate<(all_of FeatureStdExtZbkb),
"'Zbkb' (Bitmanip instructions for Cryptography)">;
@@ -487,6 +551,7 @@ def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
def FeatureStdExtZbkx
: RISCVExtension<"zbkx", 1, 0,
"'Zbkx' (Crossbar permutation instructions)">;
+def : RISCVExtensionBitmask<"zbkx", 0, 57>;
def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
AssemblerPredicate<(all_of FeatureStdExtZbkx),
"'Zbkx' (Crossbar permutation instructions)">;
@@ -504,6 +569,7 @@ def FeatureStdExtZbkc
: RISCVExtension<"zbkc", 1, 0,
"'Zbkc' (Carry-less multiply instructions for "
"Cryptography)">;
+def : RISCVExtensionBitmask<"zbkc", 0, 58>;
def HasStdExtZbkc
: Predicate<"Subtarget->hasStdExtZbkc()">,
AssemblerPredicate<(all_of FeatureStdExtZbkc),
@@ -521,6 +587,7 @@ def HasStdExtZbcOrZbkc
def FeatureStdExtZknd
: RISCVExtension<"zknd", 1, 0,
"'Zknd' (NIST Suite: AES Decryption)">;
+def : RISCVExtensionBitmask<"zknd", 0, 59>;
def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
AssemblerPredicate<(all_of FeatureStdExtZknd),
"'Zknd' (NIST Suite: AES Decryption)">;
@@ -528,6 +595,7 @@ def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
def FeatureStdExtZkne
: RISCVExtension<"zkne", 1, 0,
"'Zkne' (NIST Suite: AES Encryption)">;
+def : RISCVExtensionBitmask<"zkne", 0, 60>;
def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
AssemblerPredicate<(all_of FeatureStdExtZkne),
"'Zkne' (NIST Suite: AES Encryption)">;
@@ -543,6 +611,7 @@ def HasStdExtZkndOrZkne
def FeatureStdExtZknh
: RISCVExtension<"zknh", 1, 0,
"'Zknh' (NIST Suite: Hash Function Instructions)">;
+def : RISCVExtensionBitmask<"zknh", 0, 61>;
def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
AssemblerPredicate<(all_of FeatureStdExtZknh),
"'Zknh' (NIST Suite: Hash Function Instructions)">;
@@ -550,6 +619,7 @@ def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
def FeatureStdExtZksed
: RISCVExtension<"zksed", 1, 0,
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
+def : RISCVExtensionBitmask<"zksed", 0, 62>;
def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
AssemblerPredicate<(all_of FeatureStdExtZksed),
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
@@ -557,6 +627,7 @@ def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
def FeatureStdExtZksh
: RISCVExtension<"zksh", 1, 0,
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
+def : RISCVExtensionBitmask<"zksh", 0, 63>;
def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
AssemblerPredicate<(all_of FeatureStdExtZksh),
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
@@ -564,6 +635,7 @@ def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
def FeatureStdExtZkr
: RISCVExtension<"zkr", 1, 0,
"'Zkr' (Entropy Source Extension)">;
+def : RISCVExtensionBitmask<"zkr", 1, 0>;
def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
AssemblerPredicate<(all_of FeatureStdExtZkr),
"'Zkr' (Entropy Source Extension)">;
@@ -577,6 +649,7 @@ def FeatureStdExtZkn
FeatureStdExtZkne,
FeatureStdExtZknd,
FeatureStdExtZknh]>;
+def : RISCVExtensionBitmask<"zkn", 1, 1>;
def FeatureStdExtZks
: RISCVExtension<"zks", 1, 0,
@@ -586,10 +659,12 @@ def FeatureStdExtZks
FeatureStdExtZbkx,
FeatureStdExtZksed,
FeatureStdExtZksh]>;
+def : RISCVExtensionBitmask<"zks", 1, 2>;
def FeatureStdExtZkt
: RISCVExtension<"zkt", 1, 0,
"'Zkt' (Data Independent Execution Latency)">;
+def : RISCVExtensionBitmask<"zkt", 1, 3>;
def FeatureStdExtZk
: RISCVExtension<"zk", 1, 0,
@@ -597,12 +672,14 @@ def FeatureStdExtZk
[FeatureStdExtZkn,
FeatureStdExtZkr,
FeatureStdExtZkt]>;
+def : RISCVExtensionBitmask<"zk", 1, 4>;
// Vector Extensions
def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0,
"'Zvl' (Minimum Vector Length) 32", [],
"ZvlLen", "32">;
+def : RISCVExtensionBitmask<"zvl32b", 1, 5>;
foreach i = { 6-16 } in {
defvar I = !shl(1, i);
@@ -611,6 +688,7 @@ foreach i = { 6-16 } in {
"'Zvl' (Minimum Vector Length) "#I,
[!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],
"ZvlLen", !cast<string>(I)>;
+ def : RISCVExtensionBitmask<"zvl"#I#"b", 1, !add(6, !sub(i, 6))>;
}
def FeatureStdExtZve32x
@@ -618,40 +696,48 @@ def FeatureStdExtZve32x
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
[FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
+def : RISCVExtensionBitmask<"zve32x", 1, 17>;
+
def FeatureStdExtZve32f
: RISCVExtension<"zve32f", 1, 0,
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
[FeatureStdExtZve32x, FeatureStdExtF]>;
+def : RISCVExtensionBitmask<"zve32f", 1, 18>;
def FeatureStdExtZve64x
: RISCVExtension<"zve64x", 1, 0,
"'Zve64x' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW)",
[FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
+def : RISCVExtensionBitmask<"zve64x", 1, 19>;
def FeatureStdExtZve64f
: RISCVExtension<"zve64f", 1, 0,
"'Zve64f' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW and F extension)",
[FeatureStdExtZve32f, FeatureStdExtZve64x]>;
+def : RISCVExtensionBitmask<"zve64f", 1, 20>;
def FeatureStdExtZve64d
: RISCVExtension<"zve64d", 1, 0,
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
[FeatureStdExtZve64f, FeatureStdExtD]>;
+def : RISCVExtensionBitmask<"zve64d", 1, 21>;
def FeatureStdExtV
: RISCVExtension<"v", 1, 0,
"'V' (Vector Extension for Application Processors)",
[FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
+def : RISCVExtensionBitmask<"v", 1, 22>;
def FeatureStdExtZvfbfmin
: RISCVExperimentalExtension<"zvfbfmin", 1, 0,
"'Zvbfmin' (Vector BF16 Converts)",
[FeatureStdExtZve32f]>;
+def : RISCVExtensionBitmask<"zvfbfmin", 1, 23>;
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
"'Zvfbfmin' (Vector BF16 Converts)">;
@@ -660,6 +746,7 @@ def FeatureStdExtZvfbfwma
: RISCVExperimentalExtension<"zvfbfwma", 1, 0,
"'Zvfbfwma' (Vector BF16 widening mul-add)",
[FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
+def : RISCVExtensionBitmask<"zvfbfwma", 1, 24>;
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
@@ -668,11 +755,13 @@ def FeatureStdExtZvfhmin
: RISCVExtension<"zvfhmin", 1, 0,
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
[FeatureStdExtZve32f]>;
+def : RISCVExtensionBitmask<"zvfhmin", 1, 25>;
def FeatureStdExtZvfh
: RISCVExtension<"zvfh", 1, 0,
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>;
+def : RISCVExtensionBitmask<"zvfh", 1, 26>;
def HasStdExtZfhOrZvfh
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
@@ -685,6 +774,7 @@ def HasStdExtZfhOrZvfh
def FeatureStdExtZvkb
: RISCVExtension<"zvkb", 1, 0,
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
+def : RISCVExtensionBitmask<"zvkb", 1, 27>;
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
AssemblerPredicate<(all_of FeatureStdExtZvkb),
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
@@ -693,6 +783,7 @@ def FeatureStdExtZvbb
: RISCVExtension<"zvbb", 1, 0,
"'Zvbb' (Vector basic bit-manipulation instructions)",
[FeatureStdExtZvkb]>;
+def : RISCVExtensionBitmask<"zvbb", 1, 28>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
AssemblerPredicate<(all_of FeatureStdExtZvbb),
"'Zvbb' (Vector basic bit-manipulation instructions)">;
@@ -700,6 +791,7 @@ def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
def FeatureStdExtZvbc
: RISCVExtension<"zvbc", 1, 0,
"'Zvbc' (Vector Carryless Multiplication)">;
+def : RISCVExtensionBitmask<"zvbc", 1, 29>;
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
AssemblerPredicate<(all_of FeatureStdExtZvbc),
"'Zvbc' (Vector Carryless Multiplication)">;
@@ -707,6 +799,7 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
def FeatureStdExtZvkg
: RISCVExtension<"zvkg", 1, 0,
"'Zvkg' (Vector GCM instructions for Cryptography)">;
+def : RISCVExtensionBitmask<"zvkg", 1, 30>;
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
AssemblerPredicate<(all_of FeatureStdExtZvkg),
"'Zvkg' (Vector GCM instructions for Cryptography)">;
@@ -714,6 +807,7 @@ def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
def FeatureStdExtZvkned
: RISCVExtension<"zvkned", 1, 0,
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
+def : RISCVExtensionBitmask<"zvkned", 1, 31>;
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
AssemblerPredicate<(all_of FeatureStdExtZvkned),
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
@@ -721,6 +815,7 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
def FeatureStdExtZvknha
: RISCVExtension<"zvknha", 1, 0,
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
+def : RISCVExtensionBitmask<"zvknha", 1, 32>;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
@@ -729,6 +824,7 @@ def FeatureStdExtZvknhb
: RISCVExtension<"zvknhb", 1, 0,
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
[FeatureStdExtZve64x]>;
+def : RISCVExtensionBitmask<"zvknhb", 1, 33>;
def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
AssemblerPredicate<(all_of FeatureStdExtZvknhb),
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
@@ -740,6 +836,7 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg
def FeatureStdExtZvksed
: RISCVExtension<"zvksed", 1, 0,
"'Zvksed' (SM4 Block Cipher Instructions)">;
+def : RISCVExtensionBitmask<"zvksed", 1, 34>;
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions)">;
@@ -747,6 +844,7 @@ def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
def FeatureStdExtZvksh
: RISCVExtension<"zvksh", 1, 0,
"'Zvksh' (SM3 Hash Function Instructions)">;
+def : RISCVExtensionBitmask<"zvksh", 1, 35>;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions)">;
@@ -754,6 +852,7 @@ def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
def FeatureStdExtZvkt
: RISCVExtension<"zvkt", 1, 0,
"'Zvkt' (Vector Data-Independent Execution Latency)">;
+def : RISCVExtensionBitmask<"zvkt", 1, 36>;
// Zvk short-hand extensions
@@ -763,16 +862,19 @@ def FeatureStdExtZvkn
"'Zvkt')",
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
+def : RISCVExtensionBitmask<"zvkn", 1, 37>;
def FeatureStdExtZvknc
: RISCVExtension<"zvknc", 1, 0,
"'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
[FeatureStdExtZvkn, FeatureStdExtZvbc]>;
+def : RISCVExtensionBitmask<"zvknc", 1, 38>;
def FeatureStdExtZvkng
: RISCVExtension<"zvkng", 1, 0,
"'zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
[FeatureStdExtZvkn, FeatureStdExtZvkg]>;
+def : RISCVExtensionBitmask<"zvkng", 1, 39>;
def FeatureStdExtZvks
: RISCVExtension<"zvks", 1, 0,
@@ -780,16 +882,19 @@ def FeatureStdExtZvks
"'Zvkt')",
[FeatureStdExtZvksed, FeatureStdExtZvksh,
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
+def : RISCVExtensionBitmask<"zvks", 1, 40>;
def FeatureStdExtZvksc
: RISCVExtension<"zvksc", 1, 0,
"'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
[FeatureStdExtZvks, FeatureStdExtZvbc]>;
+def : RISCVExtensionBitmask<"zvksc", 1, 41>;
def FeatureStdExtZvksg
: RISCVExtension<"zvksg", 1, 0,
"'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
[FeatureStdExtZvks, FeatureStdExtZvkg]>;
+def : RISCVExtensionBitmask<"zvksg", 1, 42>;
// Vector instruction predicates
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 9003f9beffa7e..ec6447a44f90d 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -119,6 +119,38 @@ void getFeaturesForCPU(StringRef CPU,
else
EnabledFeatures.push_back(F.substr(1));
}
+
+namespace RISCVExtensionBitmaskTable {
+#define GET_RISCVExtensionBitmaskTable_IMPL
+#include "llvm/TargetParser/RISCVTargetParserDef.inc"
+
+} // namespace RISCVExtensionBitmaskTable
+
+namespace {
+struct LessExtName {
+ bool operator()(const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &LHS,
+ StringRef RHS) {
+ return StringRef(LHS.Name) < RHS;
+ }
+ bool
+ operator()(StringRef LHS,
+ const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &RHS) {
+ return LHS < StringRef(RHS.Name);
+ }
+};
+} // namespace
+
+static RISCVExtensionBitmaskTable::RISCVExtensionBitmask
+getExtensionBitmask(StringRef ExtName) {
+ ArrayRef<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmasks =
+ ArrayRef(RISCVExtensionBitmaskTable::ExtensionBitmask);
+ auto *I = llvm::lower_bound(ExtBitmasks, ExtName, LessExtName());
+
+ if (I != ExtBitmasks.end())
+ return *I;
+
+ return RISCVExtensionBitmaskTable::RISCVExtensionBitmask();
+}
} // namespace RISCV
namespace RISCVVType {
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index b76ba05954aa5..0c02ca626f91a 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -210,10 +210,49 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) {
OS << "\n#undef TUNE_PROC\n";
}
+static inline uint64_t getValueFromBitsInit(const BitsInit *B,
+ const Record &R) {
+ assert(B->getNumBits() <= sizeof(uint64_t) * 8 && "BitInits' too long!");
+
+ uint64_t Value = 0;
+ for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
+ const auto *Bit = dyn_cast<BitInit>(B->getBit(i));
+ if (Bit)
+ Value |= uint64_t(Bit->getValue()) << i;
+ }
+ return Value;
+}
+
+static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
+
+ std::vector<Record *> Extensions =
+ RK.getAllDerivedDefinitionsIfDefined("RISCVExtensionBitmask");
+ llvm::sort(Extensions, [](const Record *Rec1, const Record *Rec2) {
+ return getExtensionName(Rec1) < getExtensionName(Rec2);
+ });
+
+ OS << "#ifdef GET_RISCVExtensionBitmaskTable_IMPL\n";
+ OS << "static const RISCVExtensionBitmask ExtensionBitmask[]={\n";
+ for (const Record *Rec : Extensions) {
+ BitsInit *GroupIDBits = Rec->getValueAsBitsInit("GroupID");
+ BitsInit *BitmaskBits = Rec->getValueAsBitsInit("Bitmask");
+
+ assert(GroupIDBits);
+ assert(BitmaskBits);
+
+ OS << " {" << "\"" << Rec->getValueAsString("Name") << "\"" << ", "
+ << getValueFromBitsInit(GroupIDBits, *Rec) << ", "
+ << getValueFromBitsInit(BitmaskBits, *Rec) << "ULL" << "},\n";
+ }
+ OS << "};\n";
+ OS << "#endif\n";
+}
+
static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
emitRISCVExtensions(RK, OS);
emitRISCVProfiles(RK, OS);
emitRISCVProcs(RK, OS);
+ emitRISCVExtensionBitmask(RK, OS);
}
static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,
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