[llvm] [AMDGPU][WIP] Optimize SGPR spills (PR #93668)
Christudasan Devadasan via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 4 23:18:06 PDT 2024
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@@ -1775,10 +1775,13 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
if (SpillToVGPR) {
+ // Since stack slot coloring pass is trying to optimize SGPR spills,
+ // VGPR lanes (mapped from spill stack slot) may be shared for unequal SGPR
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cdevadas wrote:
Change unequal SGPR spills into SGPR spills of different sizes.
https://github.com/llvm/llvm-project/pull/93668
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