[llvm] [AMDGPU][WIP] Optimize SGPR spills (PR #93668)

[Vikash Gupta via llvm-commits]

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@@ -1775,8 +1775,10 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
 
   if (SpillToVGPR) {
 
-    assert(SB.NumSubRegs == VGPRSpills.size() &&
-           "Num of VGPR lanes should be equal to num of SGPRs spilled");
+    assert(SB.NumSubRegs <= VGPRSpills.size() &&
+           "Num of VGPR lanes should be greater or equal to num of SGPRs "
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vg0204 wrote:

I think that number of VGPR lanes corresponds to spill slot size(equal to largest spill stack object residing in it) which should be equal to or greater than number of SGPR spills created which corresponds to the spill stack object size.

https://github.com/llvm/llvm-project/pull/93668