[llvm] [PowerPC] Remove DAG matching in ADDIStocHA (PR #93905)

[Kai Luo via llvm-commits]

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@@ -3345,7 +3345,7 @@ def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor
 def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp),
                        "#ADDIStocHA",
                        [(set i32:$rD,
-                         (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>;
+                         (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
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bzEq wrote:

Yes, the scheudling is changed. Since the machineinstr succeeds the attributes from the source SDAG node from the pattern. If the pattern is removed, the machineinstr loses these attributes. For `PPCtoc_entry`, the attributes are
```
SDNPMayLoad, SDNPMemOperand
```

https://github.com/llvm/llvm-project/pull/93905