[llvm] c9a86fa - [DAG] canCreateUndefOrPoison - fix missing argument typo

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-06-02T10:34:48+01:00
New Revision: c9a86fa9a631eb77f229e457a323caec705600bf

URL: https://github.com/llvm/llvm-project/commit/c9a86fa9a631eb77f229e457a323caec705600bf
DIFF: https://github.com/llvm/llvm-project/commit/c9a86fa9a631eb77f229e457a323caec705600bf.diff

LOG: [DAG] canCreateUndefOrPoison - fix missing argument typo

We were missing the PoisonOnly argument (so Depth + 1 was being used instead and the default Depth = 0 argument then being silently used)

Fixes #94145 and serves as the test case for 9e22c7a0ea87228dffcdfd7ab62724f72e0b3e30

Added: 
    llvm/test/CodeGen/RISCV/pr94145.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 3def51c49f3a3..414c724b94f7b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5286,7 +5286,7 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
     // If the max shift amount isn't in range, then the shift can
     // create poison.
     return !isGuaranteedNotToBeUndefOrPoison(Op.getOperand(1), DemandedElts,
-                                             Depth + 1) ||
+                                             PoisonOnly, Depth + 1) ||
            !getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1);
 
   case ISD::SCALAR_TO_VECTOR:

diff  --git a/llvm/test/CodeGen/RISCV/pr94145.ll b/llvm/test/CodeGen/RISCV/pr94145.ll
new file mode 100644
index 0000000000000..17e355a9243d8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr94145.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv32-- | FileCheck %s
+; RUN: llc < %s -mtriple=riscv64-- | FileCheck %s
+
+define i32 @PR94145(i16 %a0) {
+; CHECK-LABEL: PR94145:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 2
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    li a1, 1
+; CHECK-NEXT:    sll a0, a1, a0
+; CHECK-NEXT:    ret
+  %lshr = lshr i16 %a0, 1
+  %and = and i16 %lshr, 1
+  %xor = xor i16 %and, 1
+  %shl = shl i16 1, %xor
+  %freeze = freeze i16 %shl
+  %zext = zext i16 %freeze to i32
+  ret i32 %zext
+}