[llvm] 47fd32f - [DAGCombine] Fix type mismatch in `(shl X, cttz(Y)) -> (mul (Y & -Y), X)` (#94008)
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Sat Jun 1 04:04:59 PDT 2024
Author: Yingwei Zheng
Date: 2024-06-01T19:04:55+08:00
New Revision: 47fd32f81c593ae698765e3f3f13998ac9a9abbf
URL: https://github.com/llvm/llvm-project/commit/47fd32f81c593ae698765e3f3f13998ac9a9abbf
DIFF: https://github.com/llvm/llvm-project/commit/47fd32f81c593ae698765e3f3f13998ac9a9abbf.diff
LOG: [DAGCombine] Fix type mismatch in `(shl X, cttz(Y)) -> (mul (Y & -Y), X)` (#94008)
Proof: https://alive2.llvm.org/ce/z/J7GBMU
Same as https://github.com/llvm/llvm-project/pull/92753, the types of
LHS and RHS in shift nodes may differ.
+ When VT is smaller than ShiftVT, it is safe to use trunc.
+ When VT is larger than ShiftVT, it is safe to use zext iff
`is_zero_poison` is true (i.e., `opcode == ISD::CTTZ_ZERO_UNDEF`). See
also the counterexample `src_shl_cttz2 -> tgt_shl_cttz2` in the alive2
proofs.
Fixes issue
https://github.com/llvm/llvm-project/pull/85066#issuecomment-2142553617.
Added:
llvm/test/CodeGen/PowerPC/pr85066.ll
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4debebf304412..5148b7258257f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10120,13 +10120,16 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// fold (shl X, cttz(Y)) -> (mul (Y & -Y), X) if cttz is unsupported on the
// target.
- if ((N1.getOpcode() == ISD::CTTZ || N1.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
- N1.hasOneUse() && !TLI.isOperationLegalOrCustom(ISD::CTTZ, VT) &&
+ if (((N1.getOpcode() == ISD::CTTZ &&
+ VT.getScalarSizeInBits() >= ShiftVT.getScalarSizeInBits()) ||
+ N1.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
+ N1.hasOneUse() && !TLI.isOperationLegalOrCustom(ISD::CTTZ, ShiftVT) &&
TLI.isOperationLegalOrCustom(ISD::MUL, VT)) {
SDValue Y = N1.getOperand(0);
SDLoc DL(N);
- SDValue NegY = DAG.getNegative(Y, DL, VT);
- SDValue And = DAG.getNode(ISD::AND, DL, VT, Y, NegY);
+ SDValue NegY = DAG.getNegative(Y, DL, ShiftVT);
+ SDValue And =
+ DAG.getZExtOrTrunc(DAG.getNode(ISD::AND, DL, ShiftVT, Y, NegY), DL, VT);
return DAG.getNode(ISD::MUL, DL, VT, And, N0);
}
diff --git a/llvm/test/CodeGen/PowerPC/pr85066.ll b/llvm/test/CodeGen/PowerPC/pr85066.ll
new file mode 100644
index 0000000000000..335038ec4734c
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pr85066.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=powerpc64le < %s | FileCheck %s
+
+; Tests from pr85066
+define i64 @test_shl_zext_cttz(i16 %x) {
+; CHECK-LABEL: test_shl_zext_cttz:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: oris 3, 3, 1
+; CHECK-NEXT: neg 4, 3
+; CHECK-NEXT: and 3, 3, 4
+; CHECK-NEXT: clrldi 3, 3, 32
+; CHECK-NEXT: blr
+entry:
+ %cttz = tail call i16 @llvm.cttz.i16(i16 %x, i1 false)
+ %zext = zext i16 %cttz to i64
+ %res = shl i64 1, %zext
+ ret i64 %res
+}
+
+define i64 @test_shl_zext_cttz_zero_is_poison(i16 %x) {
+; CHECK-LABEL: test_shl_zext_cttz_zero_is_poison:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: neg 4, 3
+; CHECK-NEXT: and 3, 3, 4
+; CHECK-NEXT: clrldi 3, 3, 32
+; CHECK-NEXT: blr
+entry:
+ %cttz = tail call i16 @llvm.cttz.i16(i16 %x, i1 true)
+ %zext = zext i16 %cttz to i64
+ %res = shl i64 1, %zext
+ ret i64 %res
+}
+
+define i16 @test_shl_trunc_cttz(i32 %x) {
+; CHECK-LABEL: test_shl_trunc_cttz:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: neg 4, 3
+; CHECK-NEXT: and 3, 3, 4
+; CHECK-NEXT: blr
+entry:
+ %cttz = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+ %trunc = trunc i32 %cttz to i16
+ %res = shl i16 1, %trunc
+ ret i16 %res
+}
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