[llvm] f3444f6 - [RISCV] Fix incorrect use of TA in some tablegen class names. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri May 31 20:15:30 PDT 2024
Author: Craig Topper
Date: 2024-05-31T20:13:08-07:00
New Revision: f3444f650c7bf69456c554befa65cbebe8d41e91
URL: https://github.com/llvm/llvm-project/commit/f3444f650c7bf69456c554befa65cbebe8d41e91
DIFF: https://github.com/llvm/llvm-project/commit/f3444f650c7bf69456c554befa65cbebe8d41e91.diff
LOG: [RISCV] Fix incorrect use of TA in some tablegen class names. NFC
These either have an explicit policy operand or use TU policy.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index cef926108e3ab..21c3f1b9c54c6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -4237,16 +4237,16 @@ class VPatBinaryMask<string intrinsic_name,
(op2_type op2_kind:$rs2),
(mask_type V0), GPR:$vl, sew)>;
-class VPatBinaryMaskTA<string intrinsic_name,
- string inst,
- ValueType result_type,
- ValueType op1_type,
- ValueType op2_type,
- ValueType mask_type,
- int sew,
- VReg result_reg_class,
- VReg op1_reg_class,
- DAGOperand op2_kind> :
+class VPatBinaryMaskPolicy<string intrinsic_name,
+ string inst,
+ ValueType result_type,
+ ValueType op1_type,
+ ValueType op2_type,
+ ValueType mask_type,
+ int sew,
+ VReg result_reg_class,
+ VReg op1_reg_class,
+ DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
(result_type result_reg_class:$merge),
(op1_type op1_reg_class:$rs1),
@@ -4812,9 +4812,9 @@ multiclass VPatBinary<string intrinsic,
DAGOperand op2_kind> {
def : VPatBinaryNoMaskTU<intrinsic, inst, result_type, op1_type, op2_type,
sew, result_reg_class, op1_reg_class, op2_kind>;
- def : VPatBinaryMaskTA<intrinsic, inst, result_type, op1_type, op2_type,
- mask_type, sew, result_reg_class, op1_reg_class,
- op2_kind>;
+ def : VPatBinaryMaskPolicy<intrinsic, inst, result_type, op1_type, op2_type,
+ mask_type, sew, result_reg_class, op1_reg_class,
+ op2_kind>;
}
multiclass VPatBinaryRoundingMode<string intrinsic,
@@ -4920,17 +4920,17 @@ multiclass VPatBinaryMaskOut<string intrinsic,
GPR:$vl, sew)>;
}
-multiclass VPatConversionTA<string intrinsic,
- string inst,
- string kind,
- ValueType result_type,
- ValueType op1_type,
- ValueType mask_type,
- int log2sew,
- LMULInfo vlmul,
- VReg result_reg_class,
- VReg op1_reg_class,
- bit isSEWAware = 0> {
+multiclass VPatConversion<string intrinsic,
+ string inst,
+ string kind,
+ ValueType result_type,
+ ValueType op1_type,
+ ValueType mask_type,
+ int log2sew,
+ LMULInfo vlmul,
+ VReg result_reg_class,
+ VReg op1_reg_class,
+ bit isSEWAware = 0> {
def : VPatUnaryNoMask<intrinsic, inst, kind, result_type, op1_type,
log2sew, vlmul, result_reg_class, op1_reg_class,
isSEWAware>;
@@ -4939,17 +4939,17 @@ multiclass VPatConversionTA<string intrinsic,
isSEWAware>;
}
-multiclass VPatConversionTARoundingMode<string intrinsic,
- string inst,
- string kind,
- ValueType result_type,
- ValueType op1_type,
- ValueType mask_type,
- int log2sew,
- LMULInfo vlmul,
- VReg result_reg_class,
- VReg op1_reg_class,
- bit isSEWAware = 0> {
+multiclass VPatConversionRoundingMode<string intrinsic,
+ string inst,
+ string kind,
+ ValueType result_type,
+ ValueType op1_type,
+ ValueType mask_type,
+ int log2sew,
+ LMULInfo vlmul,
+ VReg result_reg_class,
+ VReg op1_reg_class,
+ bit isSEWAware = 0> {
def : VPatUnaryNoMaskRoundingMode<intrinsic, inst, kind, result_type, op1_type,
log2sew, vlmul, result_reg_class,
op1_reg_class, isSEWAware>;
@@ -5173,10 +5173,10 @@ multiclass VPatBinaryW_WV<string intrinsic, string instruction,
Wti.Vector, Vti.Vector, Vti.Mask,
Vti.Log2SEW, Wti.RegClass, Vti.RegClass>;
}
- def : VPatBinaryMaskTA<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
- Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
- Vti.Log2SEW, Wti.RegClass,
- Wti.RegClass, Vti.RegClass>;
+ def : VPatBinaryMaskPolicy<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
+ Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
+ Vti.Log2SEW, Wti.RegClass,
+ Wti.RegClass, Vti.RegClass>;
}
}
}
@@ -5930,9 +5930,9 @@ multiclass VPatConversionVI_VF<string intrinsic,
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<ivti>.Predicates) in
- defm : VPatConversionTA<intrinsic, instruction, "V",
- ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
- fvti.LMul, ivti.RegClass, fvti.RegClass>;
+ defm : VPatConversion<intrinsic, instruction, "V",
+ ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
+ fvti.LMul, ivti.RegClass, fvti.RegClass>;
}
}
@@ -5942,9 +5942,9 @@ multiclass VPatConversionVI_VF_RM<string intrinsic,
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<ivti>.Predicates) in
- defm : VPatConversionTARoundingMode<intrinsic, instruction, "V",
- ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
- fvti.LMul, ivti.RegClass, fvti.RegClass>;
+ defm : VPatConversionRoundingMode<intrinsic, instruction, "V",
+ ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
+ fvti.LMul, ivti.RegClass, fvti.RegClass>;
}
}
@@ -5954,10 +5954,10 @@ multiclass VPatConversionVF_VI_RM<string intrinsic, string instruction,
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<ivti>.Predicates) in
- defm : VPatConversionTARoundingMode<intrinsic, instruction, "V",
- fvti.Vector, ivti.Vector, fvti.Mask, ivti.Log2SEW,
- ivti.LMul, fvti.RegClass, ivti.RegClass,
- isSEWAware>;
+ defm : VPatConversionRoundingMode<intrinsic, instruction, "V",
+ fvti.Vector, ivti.Vector, fvti.Mask, ivti.Log2SEW,
+ ivti.LMul, fvti.RegClass, ivti.RegClass,
+ isSEWAware>;
}
}
@@ -5967,9 +5967,9 @@ multiclass VPatConversionWI_VF<string intrinsic, string instruction> {
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<iwti>.Predicates) in
- defm : VPatConversionTA<intrinsic, instruction, "V",
- iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
- fvti.LMul, iwti.RegClass, fvti.RegClass>;
+ defm : VPatConversion<intrinsic, instruction, "V",
+ iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
+ fvti.LMul, iwti.RegClass, fvti.RegClass>;
}
}
@@ -5979,9 +5979,9 @@ multiclass VPatConversionWI_VF_RM<string intrinsic, string instruction> {
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<iwti>.Predicates) in
- defm : VPatConversionTARoundingMode<intrinsic, instruction, "V",
- iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
- fvti.LMul, iwti.RegClass, fvti.RegClass>;
+ defm : VPatConversionRoundingMode<intrinsic, instruction, "V",
+ iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
+ fvti.LMul, iwti.RegClass, fvti.RegClass>;
}
}
@@ -5992,9 +5992,9 @@ multiclass VPatConversionWF_VI<string intrinsic, string instruction,
defvar fwti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
- defm : VPatConversionTA<intrinsic, instruction, "V",
- fwti.Vector, vti.Vector, fwti.Mask, vti.Log2SEW,
- vti.LMul, fwti.RegClass, vti.RegClass, isSEWAware>;
+ defm : VPatConversion<intrinsic, instruction, "V",
+ fwti.Vector, vti.Vector, fwti.Mask, vti.Log2SEW,
+ vti.LMul, fwti.RegClass, vti.RegClass, isSEWAware>;
}
}
@@ -6007,35 +6007,35 @@ multiclass VPatConversionWF_VF<string intrinsic, string instruction,
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
!listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<fwti>.Predicates)) in
- defm : VPatConversionTA<intrinsic, instruction, "V",
- fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
- fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
+ defm : VPatConversion<intrinsic, instruction, "V",
+ fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
+ fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
}
}
-multiclass VPatConversionWF_VF_BF <string intrinsic, string instruction,
- bit isSEWAware = 0> {
+multiclass VPatConversionWF_VF_BF<string intrinsic, string instruction,
+ bit isSEWAware = 0> {
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in
{
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
- defm : VPatConversionTA<intrinsic, instruction, "V",
- fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
- fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
+ defm : VPatConversion<intrinsic, instruction, "V",
+ fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
+ fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
}
}
-multiclass VPatConversionVI_WF <string intrinsic, string instruction> {
+multiclass VPatConversionVI_WF<string intrinsic, string instruction> {
foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
- defm : VPatConversionTA<intrinsic, instruction, "W",
- vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
- vti.LMul, vti.RegClass, fwti.RegClass>;
+ defm : VPatConversion<intrinsic, instruction, "W",
+ vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
+ vti.LMul, vti.RegClass, fwti.RegClass>;
}
}
@@ -6045,9 +6045,9 @@ multiclass VPatConversionVI_WF_RM <string intrinsic, string instruction> {
defvar fwti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
- defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
- vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
- vti.LMul, vti.RegClass, fwti.RegClass>;
+ defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
+ vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
+ vti.LMul, vti.RegClass, fwti.RegClass>;
}
}
@@ -6058,10 +6058,10 @@ multiclass VPatConversionVF_WI_RM <string intrinsic, string instruction,
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<iwti>.Predicates) in
- defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
- fvti.Vector, iwti.Vector, fvti.Mask, fvti.Log2SEW,
- fvti.LMul, fvti.RegClass, iwti.RegClass,
- isSEWAware>;
+ defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
+ fvti.Vector, iwti.Vector, fvti.Mask, fvti.Log2SEW,
+ fvti.LMul, fvti.RegClass, iwti.RegClass,
+ isSEWAware>;
}
}
@@ -6072,9 +6072,9 @@ multiclass VPatConversionVF_WF<string intrinsic, string instruction,
defvar fwti = fvtiToFWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
- defm : VPatConversionTA<intrinsic, instruction, "W",
- fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
- fvti.LMul, fvti.RegClass, fwti.RegClass, isSEWAware>;
+ defm : VPatConversion<intrinsic, instruction, "W",
+ fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
+ fvti.LMul, fvti.RegClass, fwti.RegClass, isSEWAware>;
}
}
@@ -6086,24 +6086,24 @@ multiclass VPatConversionVF_WF_RM<string intrinsic, string instruction,
defvar fwti = fvtiToFWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
- defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
- fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
- fvti.LMul, fvti.RegClass, fwti.RegClass,
- isSEWAware>;
+ defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
+ fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
+ fvti.LMul, fvti.RegClass, fwti.RegClass,
+ isSEWAware>;
}
}
-multiclass VPatConversionVF_WF_BF_RM <string intrinsic, string instruction,
- bit isSEWAware = 0> {
+multiclass VPatConversionVF_WF_BF_RM<string intrinsic, string instruction,
+ bit isSEWAware = 0> {
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
- defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
- fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
- fvti.LMul, fvti.RegClass, fwti.RegClass,
- isSEWAware>;
+ defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
+ fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
+ fvti.LMul, fvti.RegClass, fwti.RegClass,
+ isSEWAware>;
}
}
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