[llvm] [AArch64] Replace AND with LSL#2 for LDR target (#34101) (PR #89531)

[Justin Fargnoli via llvm-commits]

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@@ -28338,6 +28340,50 @@ bool DAGCombiner::findBetterNeighborChains(StoreSDNode *St) {
   return false;
 }
 
+bool DAGCombiner::isCanBeLoadedWithLsl(SDNode *N) {
+  if (!N->hasOneUse())
+    return false;
+
+  APInt SrlAmt;
+  if (sd_match(N,
+               m_Shl(m_Srl(m_Value(), m_ConstInt(SrlAmt)), m_SpecificInt(2)))) {
+    // Srl knownbits
+    SDValue ShlV = SDValue(N, 0);
+    unsigned RegSize = ShlV.getValueType().getScalarSizeInBits();
+    KnownBits Known = DAG.computeKnownBits(ShlV);
+    if (Known.getBitWidth() != RegSize)
+      return false;
+
+    // check load (ldr x, (add x, (shl (srl x, c1) 2)))
+    SDNode *User = N->use_begin().getUse().getUser();
+    if (!User || User->getOpcode() != ISD::ADD)
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justinfargnoli wrote:

Nit: You could use [`dyn_cast_or_null`](https://llvm.org/docs/ProgrammersManual.html#the-isa-cast-and-dyn-cast-templates). 

https://github.com/llvm/llvm-project/pull/89531