[llvm] [RISCV] Match strided vector bases in RISCVGatherScatterLowering (PR #93972)

[Luke Lau via llvm-commits]

lukel97 wrote:

> I do understand that this is more general peephole optimization, but more accurate one will be to teach vectorizer to emit strided intrinsics, like (vp.strided.load)[https://llvm.org/docs/LangRef.html#llvm-experimental-vp-strided-load-intrinsic]. Or, otherwise, provide indexes analysis that cost model can use to accurately estimate such accesses.
> 
> JFYI: we have a plan to upstream support of strided accesses for EVL vectorization by leveraging these intrinsics.

I was discussing this offline with @preames and we're in agreement here, relying on RISCVGatherScatterLowering to catch these widened loads and stores is fragile. But teaching the loop vectorizer to emit llvm.experimental.vp.strided.{load,store} is a bigger piece of work so this is just a stopgap in the meantime.

Also there's still 2054 v[ls][uo]xei instructions emitted on SPEC after this patch, and I presume some of those are strided acceses that are still slipping through the cracks.

https://github.com/llvm/llvm-project/pull/93972