[llvm] [AMDGPU][NFC] Eliminate GCNPredicateControl. (PR #93964)
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Fri May 31 07:02:44 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Ivan Kosarev (kosarev)
<details>
<summary>Changes</summary>
Removes ~100K instances of SIAssemblerPredicate and VIAssemblerPredicate fields from instruction records.
---
Full diff: https://github.com/llvm/llvm-project/pull/93964.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInstrFormats.td (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.td (+2-7)
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+1-3)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index 327eb89efcb88..1fe8beafd5e5d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -12,7 +12,7 @@
class InstSI <dag outs, dag ins, string asm = "",
list<dag> pattern = []> :
- AMDGPUInst<outs, ins, asm, pattern>, GCNPredicateControl {
+ AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
// Low bits - basic encoding information.
field bit SALU = 0;
field bit VALU = 0;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index fd119e0992e56..3dad7ec0100de 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -11,13 +11,8 @@ def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,
def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
AssemblerPredicate <(all_of FeatureWavefrontSize64)>;
-class GCNPredicateControl : PredicateControl {
- Predicate SIAssemblerPredicate = isGFX6GFX7;
- Predicate VIAssemblerPredicate = isGFX8GFX9;
-}
-
class AMDGPUMnemonicAlias<string From, string To, string VariantName = "">
- : MnemonicAlias<From, To, VariantName>, GCNPredicateControl;
+ : MnemonicAlias<From, To, VariantName>, PredicateControl;
// Except for the NONE field, this must be kept in sync with the
// SIEncodingFamily enum in SIInstrInfo.cpp and the columns of the
@@ -2670,7 +2665,7 @@ class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
VINTRPCommon <outs, ins, asm, []>,
VINTRPe_vi <op>,
SIMCInstr<opName, SIEncodingFamily.VI> {
- let AssemblerPredicate = VIAssemblerPredicate;
+ let AssemblerPredicate = isGFX8GFX9;
let DecoderNamespace = "GFX8";
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index d1667955f83db..c1b844f844c32 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -10,9 +10,7 @@
// that are not yet supported remain commented out.
//===----------------------------------------------------------------------===//
-class GCNPat<dag pattern, dag result> : Pat<pattern, result>, GCNPredicateControl {
-
-}
+class GCNPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl;
class UniformSextInreg<ValueType VT> : PatFrag<
(ops node:$src),
``````````
</details>
https://github.com/llvm/llvm-project/pull/93964
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