[llvm] [MCA] Parameterize variant scheduling classes by explicit variable (PR #92849)

[Michael Maitland via llvm-commits]

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@@ -111,8 +112,15 @@ class InstrBuilder {
   /// or null if there isn't any.
   void setInstRecycleCallback(InstRecycleCallback CB) { InstRecycleCB = CB; }
 
+  /// Create an MCA Instruction from a MC Instruction that contains all the
+  /// relevant state MCA needs for modeling. Variant instructions (e.g.,
+  /// register zeroing idioms) each need their own instruction description
+  /// which is uniqued based on InstructionAddress. This can be an actual
+  /// address or something unique per instruction like a loop iteration
+  /// variable, but it must uniquely identify the instruction being passed in.
   Expected<std::unique_ptr<Instruction>>
-  createInstruction(const MCInst &MCI, const SmallVector<Instrument *> &IVec);
+  createInstruction(const MCInst &MCI, const SmallVector<Instrument *> &IVec,
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michaelmaitland wrote:

> Wouldn't that just be equivalent to creating a new variant description for each MCInst? We can structure it like that, but that seems to defeat the point of the cache.

I see us using different `InstructionAddress` for each `createInstruction` call. I suggested this because I thought the test case was showing us how this patch is intended to be useful. Do we need to modify the test to show the behavior of getting the instruction from the cache by passing the same `{MCInst, InstructionAddress}` pair?

https://github.com/llvm/llvm-project/pull/92849