[llvm] [MCA] Parameterize variant scheduling classes by explicit variable (PR #92849)

[Michael Maitland via llvm-commits]

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@@ -185,3 +188,51 @@ TEST_F(X86TestBase, TestInstructionRecycling) {
     ASSERT_EQ(*BV, *V) << "Value of '" << F << "' does not match";
   }
 }
+
+// Test that we do not depend upon the MCInst address for variant description
+// construction. This test creates two instructions that will use variant
+// description as they are both zeroing idioms, but write to different
+// registers. If the key used to access the variant instruction description is
+// the same between the descriptions (like the MCInst pointer), we will run into
+// an assertion failure due to the different writes. Within this test, setting
+// both instruction addresses to the same builder within the calls to the MCA
+// instruction builder will cause the problem.
+TEST_F(X86TestBase, TestVariantInstructionsSameAddress) {
+  mca::Context MCA(*MRI, *STI);
+
+  mca::IncrementalSourceMgr ISM;
+  // Empty CustomBehavioour.
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michaelmaitland wrote:

nit: spelling

https://github.com/llvm/llvm-project/pull/92849