[llvm] 5f243b3 - AMDGPU: Generalize instruction shrinking code (#93810)
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Thu May 30 10:25:08 PDT 2024
Author: Matt Arsenault
Date: 2024-05-30T19:25:04+02:00
New Revision: 5f243b3fffca42ed320529a54aefd86087aa85f8
URL: https://github.com/llvm/llvm-project/commit/5f243b3fffca42ed320529a54aefd86087aa85f8
DIFF: https://github.com/llvm/llvm-project/commit/5f243b3fffca42ed320529a54aefd86087aa85f8.diff
LOG: AMDGPU: Generalize instruction shrinking code (#93810)
Try to avoid referring to specific operand names, except in the special
case. The special case for hasNamedOperand(Op32, sdst) seems to have
been dead code.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index bb5f166e47925..779f4c853326d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4486,46 +4486,46 @@ static void copyFlagsToImplicitVCC(MachineInstr &MI,
MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,
unsigned Op32) const {
MachineBasicBlock *MBB = MI.getParent();
+
+ const MCInstrDesc &Op32Desc = get(Op32);
MachineInstrBuilder Inst32 =
- BuildMI(*MBB, MI, MI.getDebugLoc(), get(Op32))
+ BuildMI(*MBB, MI, MI.getDebugLoc(), Op32Desc)
.setMIFlags(MI.getFlags());
// Add the dst operand if the 32-bit encoding also has an explicit $vdst.
// For VOPC instructions, this is replaced by an implicit def of vcc.
- if (AMDGPU::hasNamedOperand(Op32, AMDGPU::OpName::vdst)) {
- // dst
- Inst32.add(MI.getOperand(0));
- } else if (AMDGPU::hasNamedOperand(Op32, AMDGPU::OpName::sdst)) {
- // VOPCX instructions won't be writing to an explicit dst, so this should
- // not fail for these instructions.
- assert(((MI.getOperand(0).getReg() == AMDGPU::VCC) ||
- (MI.getOperand(0).getReg() == AMDGPU::VCC_LO)) &&
- "Unexpected case");
- }
-
- Inst32.add(*getNamedOperand(MI, AMDGPU::OpName::src0));
- const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
- if (Src1)
- Inst32.add(*Src1);
+ // We assume the defs of the shrunk opcode are in the same order, and the
+ // shrunk opcode loses the last def (SGPR def, in the VOP3->VOPC case).
+ for (int I = 0, E = Op32Desc.getNumDefs(); I != E; ++I)
+ Inst32.add(MI.getOperand(I));
const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
- if (Src2) {
- int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
- if (Op32Src2Idx != -1) {
- Inst32.add(*Src2);
- } else {
- // In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
- // replaced with an implicit read of vcc or vcc_lo. The implicit read
- // of vcc was already added during the initial BuildMI, but we
- // 1) may need to change vcc to vcc_lo to preserve the original register
- // 2) have to preserve the original flags.
- fixImplicitOperands(*Inst32);
- copyFlagsToImplicitVCC(*Inst32, *Src2);
+ int Idx = MI.getNumExplicitDefs();
+ for (const MachineOperand &Use : MI.explicit_uses()) {
+ int OpTy = MI.getDesc().operands()[Idx++].OperandType;
+ if (OpTy == AMDGPU::OPERAND_INPUT_MODS || OpTy == MCOI::OPERAND_IMMEDIATE)
+ continue;
+
+ if (&Use == Src2) {
+ if (AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2) == -1) {
+ // In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
+ // replaced with an implicit read of vcc or vcc_lo. The implicit read
+ // of vcc was already added during the initial BuildMI, but we
+ // 1) may need to change vcc to vcc_lo to preserve the original register
+ // 2) have to preserve the original flags.
+ fixImplicitOperands(*Inst32);
+ copyFlagsToImplicitVCC(*Inst32, *Src2);
+ continue;
+ }
}
+
+ Inst32.add(Use);
}
+ // FIXME: Losing implicit operands
+
return Inst32;
}
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