[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[via llvm-commits]

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@@ -133,6 +133,12 @@ struct Instruction {
   // aliasing Use and Def registers.
   bool hasAliasingRegisters(const BitVector &ForbiddenRegisters) const;
 
+  // Whether this instruction is self aliasing through some registers.
+  // Repeating this instruction may execute sequentially by picking aliasing
+  // Def and Not Memory Use registers. It may also execute in parallel by
+  // picking non aliasing Def and Not Memory Use registers.
+  bool hasAliasingNotMemoryRegisters(const BitVector &ForbiddenRegisters) const;
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AnastasiyaChernikova wrote:

This function use to enable alternative strategy for instructions with memory operands. We have tests to cheek this behavior in `test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s`

https://github.com/llvm/llvm-project/pull/89047