[llvm] [GISel] Convert zext nneg to sext if it is cheaper (PR #93842)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Thu May 30 09:24:41 PDT 2024
https://github.com/dtcxzyw created https://github.com/llvm/llvm-project/pull/93842
The logic is copied from SelectionDAGBuilder:
https://github.com/llvm/llvm-project/blob/32546bd2ff822df2419589a03747c6d83415a59e/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp#L3829-L3836
>From 19d35de3678da150d5f6e2424965d1a30fe26b87 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Thu, 30 May 2024 23:34:52 +0800
Subject: [PATCH 1/2] [RISCV][GISel] Add pre-commit tests. NFC.
---
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 11 +++++++++++
.../RISCV/GlobalISel/alu-roundtrip-rv64.ll | 11 +++++++++++
.../GlobalISel/irtranslator/zext-nneg-rv64.ll | 18 ++++++++++++++++++
3 files changed, 40 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/zext-nneg-rv64.ll
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 5289b993476db..8c9a6a1f4132b 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1569,6 +1569,17 @@ bool IRTranslator::translateCast(unsigned Opcode, const User &U,
Register Op = getOrCreateVReg(*U.getOperand(0));
Register Res = getOrCreateVReg(U);
+
+ // Convert zext nneg to sext if it is preferred form for the target.
+ // if (Opcode == TargetOpcode::G_ZEXT && (Flags & MachineInstr::NonNeg)) {
+ // EVT SrcVT = TLI->getValueType(*DL, U.getOperand(0)->getType());
+ // EVT DstVT = TLI->getValueType(*DL, U.getType());
+ // if (TLI->isSExtCheaperThanZExt(SrcVT, DstVT)) {
+ // Opcode = TargetOpcode::G_SEXT;
+ // Flags = 0;
+ // }
+ // }
+
MIRBuilder.buildInstr(Opcode, {Res}, {Op}, Flags);
return true;
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip-rv64.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip-rv64.ll
index d4acca17930d5..df3be2ef1f933 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip-rv64.ll
@@ -101,3 +101,14 @@ entry:
%0 = urem i64 %a, %b
ret i64 %0
}
+
+define i64 @zext_nneg_i32_i64(i32 %a) {
+; RV64IM-LABEL: zext_nneg_i32_i64:
+; RV64IM: # %bb.0: # %entry
+; RV64IM-NEXT: slli a0, a0, 32
+; RV64IM-NEXT: srli a0, a0, 32
+; RV64IM-NEXT: ret
+entry:
+ %b = zext nneg i32 %a to i64
+ ret i64 %b
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/zext-nneg-rv64.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/zext-nneg-rv64.ll
new file mode 100644
index 0000000000000..298413ee55d35
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/zext-nneg-rv64.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
+
+define i64 @zext_nneg_i32_i64(i32 %a) {
+ ; RV64I-LABEL: name: zext_nneg_i32_i64
+ ; RV64I: bb.1.entry:
+ ; RV64I-NEXT: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; RV64I-NEXT: %2:_(s64) = nneg G_ZEXT [[TRUNC]](s32)
+ ; RV64I-NEXT: $x10 = COPY %2(s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+entry:
+ %b = zext nneg i32 %a to i64
+ ret i64 %b
+}
>From cd72dbab45f434dfdada262e1ea728356d2abec0 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Fri, 31 May 2024 00:12:31 +0800
Subject: [PATCH 2/2] [GISel] Convert zext nneg to sext if it is cheaper
---
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 16 ++++++++--------
.../RISCV/GlobalISel/alu-roundtrip-rv64.ll | 3 +--
.../GlobalISel/irtranslator/zext-nneg-rv64.ll | 4 ++--
3 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 8c9a6a1f4132b..d5138c68218c1 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1571,14 +1571,14 @@ bool IRTranslator::translateCast(unsigned Opcode, const User &U,
Register Res = getOrCreateVReg(U);
// Convert zext nneg to sext if it is preferred form for the target.
- // if (Opcode == TargetOpcode::G_ZEXT && (Flags & MachineInstr::NonNeg)) {
- // EVT SrcVT = TLI->getValueType(*DL, U.getOperand(0)->getType());
- // EVT DstVT = TLI->getValueType(*DL, U.getType());
- // if (TLI->isSExtCheaperThanZExt(SrcVT, DstVT)) {
- // Opcode = TargetOpcode::G_SEXT;
- // Flags = 0;
- // }
- // }
+ if (Opcode == TargetOpcode::G_ZEXT && (Flags & MachineInstr::NonNeg)) {
+ EVT SrcVT = TLI->getValueType(*DL, U.getOperand(0)->getType());
+ EVT DstVT = TLI->getValueType(*DL, U.getType());
+ if (TLI->isSExtCheaperThanZExt(SrcVT, DstVT)) {
+ Opcode = TargetOpcode::G_SEXT;
+ Flags = 0;
+ }
+ }
MIRBuilder.buildInstr(Opcode, {Res}, {Op}, Flags);
return true;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip-rv64.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip-rv64.ll
index df3be2ef1f933..fd80afce6510e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip-rv64.ll
@@ -105,8 +105,7 @@ entry:
define i64 @zext_nneg_i32_i64(i32 %a) {
; RV64IM-LABEL: zext_nneg_i32_i64:
; RV64IM: # %bb.0: # %entry
-; RV64IM-NEXT: slli a0, a0, 32
-; RV64IM-NEXT: srli a0, a0, 32
+; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: ret
entry:
%b = zext nneg i32 %a to i64
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/zext-nneg-rv64.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/zext-nneg-rv64.ll
index 298413ee55d35..2e37da0c03a51 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/zext-nneg-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/zext-nneg-rv64.ll
@@ -9,8 +9,8 @@ define i64 @zext_nneg_i32_i64(i32 %a) {
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64I-NEXT: %2:_(s64) = nneg G_ZEXT [[TRUNC]](s32)
- ; RV64I-NEXT: $x10 = COPY %2(s64)
+ ; RV64I-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[SEXT]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
entry:
%b = zext nneg i32 %a to i64
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