[llvm] [PowerPC] Adjust operand order of ADDItoc to be consistent with other ADDI* nodes. NFC. (PR #93642)

Sean Fertile via llvm-commits llvm-commits at lists.llvm.org
Thu May 30 09:02:50 PDT 2024


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@@ -1485,10 +1485,10 @@ def ADDItocL8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:
 }
 
 // Local Data Transform
-def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
+def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
                    "#ADDItoc8",
                    [(set i64:$rD,
-                     (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
+                     (PPCtoc_entry i64:$reg, tglobaladdr:$disp))]>, isPPC64;
----------------
mandlebug wrote:

Why are we changing this pattern (ditto for the `ADDItoc` pattern as well)? If this was meant to be a match pattern for a PPCtoc_entry node I belive the operands are always a target global address followed by the TOC-base register.  [here](https://github.com/llvm/llvm-project/blob/b62ba7f5b1caf99a3cbbe06d0e1c788c2dc85416/llvm/lib/Target/PowerPC/PPCISelLowering.h#L601) and [here](https://github.com/llvm/llvm-project/blob/ed35a92c404650b15a79ff38bcaff41de176cb78/llvm/lib/Target/PowerPC/PPCISelLowering.cpp#L3193)

I don't think we ever rely on pattern matching for transforming to these nodes though (since we need to manually check for the attribute on the Global Symbol), so in that case we are best to remove the pattern.

https://github.com/llvm/llvm-project/pull/93642


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