[llvm] [RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (PR #93735)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Wed May 29 13:33:30 PDT 2024
https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/93735
FLH/W/D have load latencies closer to 5 rather than 6.
>From 8052d27709ce61214cac285b883f364aeefc1e12 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Wed, 29 May 2024 13:28:20 -0700
Subject: [PATCH] [RISCV] Adjust FP load latencies from 6 to 5 in
SiFiveP400/P600 scheduling models
FLH/W/D have load latencies closer to 5 rather than 6.
---
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 2 +-
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 2 +-
.../tools/llvm-mca/RISCV/SiFiveP400/load.s | 56 ++++++++++++++++
.../tools/llvm-mca/RISCV/SiFiveP600/load.s | 64 +++++++++++++++++++
4 files changed, 122 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index 80362cae00fcd..9fa455be38525 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -140,7 +140,7 @@ def : WriteRes<WriteLDW, [SiFiveP400Load]>;
def : WriteRes<WriteLDD, [SiFiveP400Load]>;
}
-let Latency = 6 in {
+let Latency = 5 in {
def : WriteRes<WriteFLD16, [SiFiveP400Load]>;
def : WriteRes<WriteFLD32, [SiFiveP400Load]>;
def : WriteRes<WriteFLD64, [SiFiveP400Load]>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index f0697a1b0673f..ba062f33b929a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -190,7 +190,7 @@ def : WriteRes<WriteLDW, [SiFiveP600LDST]>;
def : WriteRes<WriteLDD, [SiFiveP600LDST]>;
}
-let Latency = 6 in {
+let Latency = 5 in {
def : WriteRes<WriteFLD16, [SiFiveP600LDST]>;
def : WriteRes<WriteFLD32, [SiFiveP600LDST]>;
def : WriteRes<WriteFLD64, [SiFiveP600LDST]>;
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s
new file mode 100644
index 0000000000000..3cf207b594ad9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s
@@ -0,0 +1,56 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p450 -iterations=1 < %s | FileCheck %s
+
+lw t0, 0(a0)
+ld t0, 0(a0)
+
+flh ft0, 0(a0)
+flw ft0, 0(a0)
+fld ft0, 0(a0)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 5
+# CHECK-NEXT: Total Cycles: 12
+# CHECK-NEXT: Total uOps: 5
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.42
+# CHECK-NEXT: IPC: 0.42
+# CHECK-NEXT: Block RThroughput: 5.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 1.00 * lw t0, 0(a0)
+# CHECK-NEXT: 1 4 1.00 * ld t0, 0(a0)
+# CHECK-NEXT: 1 5 1.00 * flh ft0, 0(a0)
+# CHECK-NEXT: 1 5 1.00 * flw ft0, 0(a0)
+# CHECK-NEXT: 1 5 1.00 * fld ft0, 0(a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# CHECK-NEXT: - - - - - - 5.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
+# CHECK-NEXT: - - - - - - 1.00 - lw t0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - ld t0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - flh ft0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - flw ft0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - fld ft0, 0(a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s
new file mode 100644
index 0000000000000..9ece35b92dfaa
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s
@@ -0,0 +1,64 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+lw t0, 0(a0)
+ld t0, 0(a0)
+
+flh ft0, 0(a0)
+flw ft0, 0(a0)
+fld ft0, 0(a0)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 5
+# CHECK-NEXT: Total Cycles: 10
+# CHECK-NEXT: Total uOps: 5
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.50
+# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.50 * lw t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * ld t0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * flh ft0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * flw ft0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * fld ft0, 0(a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - - - - - 2.00 3.00 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - lw t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - ld t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - flh ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - flw ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - fld ft0, 0(a0)
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