[llvm] [GISel] LegalizationArtifactCombiner: Elide redundant G_SEXT_INREG (PR #93687)

[Tobias Stadler via llvm-commits]

tobias-stadler wrote:

I quickly ran AArch64 CTMark on this for O0 and O2: compile-time instruction count difference is below the noise floor, size..text is unchanged. So this doesn't seem to regress anything for ZeroOrOneBooleanContent Targets.

When I added the zext-combine, the main reasons were huge compile-time and O0 code-size improvements for ZeroOrOneBooleanContent Targets, so it makes sense that ZeroOrNegativeOneBooleanContent Targets would see similar improvements from this commit. I do agree that using KnownBits in the ArtifactCombiner is hacky, because it can't fully replace the post-legalize version of these KnownBits combines. However, I don't see another way to efficiently handle boolean legalization, so this still seems like the most practical solution to me. That said, I believe these 2 combines should remain the only ones using KnownBits in the ArtifactCombiner. 

https://github.com/llvm/llvm-project/pull/93687