[llvm] 4e251e7 - Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-05-29T17:57:34+01:00
New Revision: 4e251e7cad6c27b7476edd8e1dc4b98d5a8efe76

URL: https://github.com/llvm/llvm-project/commit/4e251e7cad6c27b7476edd8e1dc4b98d5a8efe76
DIFF: https://github.com/llvm/llvm-project/commit/4e251e7cad6c27b7476edd8e1dc4b98d5a8efe76.diff

LOG: Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 9208b096affad..6f0cae2edab17 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -8013,7 +8013,7 @@ LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
         Tmp2 = MIRBuilder.buildLShr(Ty, Src, ShAmt);
       }
 
-      auto Mask = MIRBuilder.buildConstant(Ty, 1U << J);
+      auto Mask = MIRBuilder.buildConstant(Ty, 1ULL << J);
       Tmp2 = MIRBuilder.buildAnd(Ty, Tmp2, Mask);
       if (I == 0)
         Tmp = Tmp2;