[llvm] 886d316 - [AArch64][NFC] Pre-commit test for Push ADD/SUB through {S|Z}EXT (#90964)
Tuan Chuong Goh via llvm-commits
llvm-commits at lists.llvm.org
Wed May 29 06:46:05 PDT 2024
Author: Tuan Chuong Goh
Date: 2024-05-29T13:43:53Z
New Revision: 886d31675dbb6fe8cf97fd9083870bd043ce9f02
URL: https://github.com/llvm/llvm-project/commit/886d31675dbb6fe8cf97fd9083870bd043ce9f02
DIFF: https://github.com/llvm/llvm-project/commit/886d31675dbb6fe8cf97fd9083870bd043ce9f02.diff
LOG: [AArch64][NFC] Pre-commit test for Push ADD/SUB through {S|Z}EXT (#90964)
Added:
Modified:
llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
llvm/test/CodeGen/AArch64/neon-extadd.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
index fad3655da9d01..78411f34bebd3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
@@ -207,3 +207,122 @@ body: |
%3:_(<4 x s32>) = G_FADD %0, %2(<4 x s32>)
$q0 = COPY %3(<4 x s32>)
...
+---
+name: saddl_v8i8_v8i32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1
+
+ ; CHECK-LABEL: name: saddl_v8i8_v8i32
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[SEXT]], [[SEXT1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)
+ %3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)
+ %4:_(<8 x s32>) = G_ADD %2, %3
+ %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
+ $q0 = COPY %5(<4 x s32>)
+ $q1 = COPY %6(<4 x s32>)
+ RET_ReallyLR implicit $q0, implicit $q1
+...
+
+---
+name: uaddl_v8i8_v8i32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1
+
+ ; CHECK-LABEL: name: uaddl_v8i8_v8i32
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[ZEXT]], [[ZEXT1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)
+ %3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)
+ %4:_(<8 x s32>) = G_ADD %2, %3
+ %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
+ $q0 = COPY %5(<4 x s32>)
+ $q1 = COPY %6(<4 x s32>)
+ RET_ReallyLR implicit $q0, implicit $q1
+...
+
+---
+name: ssubl_v8i8_v8i32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1
+
+ ; CHECK-LABEL: name: ssubl_v8i8_v8i32
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[SEXT]], [[SEXT1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SUB]](<8 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)
+ %3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)
+ %4:_(<8 x s32>) = G_SUB %2, %3
+ %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
+ $q0 = COPY %5(<4 x s32>)
+ $q1 = COPY %6(<4 x s32>)
+ RET_ReallyLR implicit $q0, implicit $q1
+...
+
+---
+name: usubl_v8i8_v8i32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1
+
+ ; CHECK-LABEL: name: usubl_v8i8_v8i32
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[ZEXT]], [[ZEXT1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SUB]](<8 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)
+ %3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)
+ %4:_(<8 x s32>) = G_SUB %2, %3
+ %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
+ $q0 = COPY %5(<4 x s32>)
+ $q1 = COPY %6(<4 x s32>)
+ RET_ReallyLR implicit $q0, implicit $q1
+...
diff --git a/llvm/test/CodeGen/AArch64/neon-extadd.ll b/llvm/test/CodeGen/AArch64/neon-extadd.ll
index 16200435c5c31..6aa9c394a8fd1 100644
--- a/llvm/test/CodeGen/AArch64/neon-extadd.ll
+++ b/llvm/test/CodeGen/AArch64/neon-extadd.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple aarch64 -o - | FileCheck %s
+; RUN: llc < %s -mtriple aarch64 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple aarch64 -o - -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <8 x i16> @extadds_v8i8_i16(<8 x i8> %s0, <8 x i8> %s1) {
; CHECK-LABEL: extadds_v8i8_i16:
@@ -26,12 +27,19 @@ entry:
}
define <16 x i16> @extadds_v16i8_i16(<16 x i8> %s0, <16 x i8> %s1) {
-; CHECK-LABEL: extadds_v16i8_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl2 v2.8h, v0.16b, v1.16b
-; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: mov v1.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extadds_v16i8_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: saddl2 v2.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: saddl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v16i8_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: saddl v2.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: saddl2 v1.8h, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <16 x i8> %s0 to <16 x i16>
%s1s = sext <16 x i8> %s1 to <16 x i16>
@@ -40,12 +48,19 @@ entry:
}
define <16 x i16> @extaddu_v16i8_i16(<16 x i8> %s0, <16 x i8> %s1) {
-; CHECK-LABEL: extaddu_v16i8_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl2 v2.8h, v0.16b, v1.16b
-; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: mov v1.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extaddu_v16i8_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddl2 v2.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: uaddl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v16i8_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: uaddl v2.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: uaddl2 v1.8h, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <16 x i8> %s0 to <16 x i16>
%s1s = zext <16 x i8> %s1 to <16 x i16>
@@ -54,16 +69,26 @@ entry:
}
define <32 x i16> @extadds_v32i8_i16(<32 x i8> %s0, <32 x i8> %s1) {
-; CHECK-LABEL: extadds_v32i8_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl2 v4.8h, v1.16b, v3.16b
-; CHECK-NEXT: saddl v5.8h, v0.8b, v2.8b
-; CHECK-NEXT: saddl2 v6.8h, v0.16b, v2.16b
-; CHECK-NEXT: saddl v2.8h, v1.8b, v3.8b
-; CHECK-NEXT: mov v0.16b, v5.16b
-; CHECK-NEXT: mov v1.16b, v6.16b
-; CHECK-NEXT: mov v3.16b, v4.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extadds_v32i8_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: saddl2 v4.8h, v1.16b, v3.16b
+; CHECK-SD-NEXT: saddl v5.8h, v0.8b, v2.8b
+; CHECK-SD-NEXT: saddl2 v6.8h, v0.16b, v2.16b
+; CHECK-SD-NEXT: saddl v2.8h, v1.8b, v3.8b
+; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: mov v1.16b, v6.16b
+; CHECK-SD-NEXT: mov v3.16b, v4.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v32i8_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: saddl v4.8h, v0.8b, v2.8b
+; CHECK-GI-NEXT: saddl2 v5.8h, v0.16b, v2.16b
+; CHECK-GI-NEXT: saddl v2.8h, v1.8b, v3.8b
+; CHECK-GI-NEXT: saddl2 v3.8h, v1.16b, v3.16b
+; CHECK-GI-NEXT: mov v0.16b, v4.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <32 x i8> %s0 to <32 x i16>
%s1s = sext <32 x i8> %s1 to <32 x i16>
@@ -72,16 +97,26 @@ entry:
}
define <32 x i16> @extaddu_v32i8_i16(<32 x i8> %s0, <32 x i8> %s1) {
-; CHECK-LABEL: extaddu_v32i8_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl2 v4.8h, v1.16b, v3.16b
-; CHECK-NEXT: uaddl v5.8h, v0.8b, v2.8b
-; CHECK-NEXT: uaddl2 v6.8h, v0.16b, v2.16b
-; CHECK-NEXT: uaddl v2.8h, v1.8b, v3.8b
-; CHECK-NEXT: mov v0.16b, v5.16b
-; CHECK-NEXT: mov v1.16b, v6.16b
-; CHECK-NEXT: mov v3.16b, v4.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extaddu_v32i8_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddl2 v4.8h, v1.16b, v3.16b
+; CHECK-SD-NEXT: uaddl v5.8h, v0.8b, v2.8b
+; CHECK-SD-NEXT: uaddl2 v6.8h, v0.16b, v2.16b
+; CHECK-SD-NEXT: uaddl v2.8h, v1.8b, v3.8b
+; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: mov v1.16b, v6.16b
+; CHECK-SD-NEXT: mov v3.16b, v4.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v32i8_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: uaddl v4.8h, v0.8b, v2.8b
+; CHECK-GI-NEXT: uaddl2 v5.8h, v0.16b, v2.16b
+; CHECK-GI-NEXT: uaddl v2.8h, v1.8b, v3.8b
+; CHECK-GI-NEXT: uaddl2 v3.8h, v1.16b, v3.16b
+; CHECK-GI-NEXT: mov v0.16b, v4.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <32 x i8> %s0 to <32 x i16>
%s1s = zext <32 x i8> %s1 to <32 x i16>
@@ -90,12 +125,20 @@ entry:
}
define <8 x i32> @extadds_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1) {
-; CHECK-LABEL: extadds_v8i8_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: sshll2 v1.4s, v0.8h, #0
-; CHECK-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extadds_v8i8_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: saddl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: sshll2 v1.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v8i8_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: saddl v0.4s, v2.4h, v1.4h
+; CHECK-GI-NEXT: saddl2 v1.4s, v2.8h, v1.8h
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <8 x i8> %s0 to <8 x i32>
%s1s = sext <8 x i8> %s1 to <8 x i32>
@@ -104,12 +147,20 @@ entry:
}
define <8 x i32> @extaddu_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1) {
-; CHECK-LABEL: extaddu_v8i8_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ushll2 v1.4s, v0.8h, #0
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extaddu_v8i8_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
+; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v8i8_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: uaddl v0.4s, v2.4h, v1.4h
+; CHECK-GI-NEXT: uaddl2 v1.4s, v2.8h, v1.8h
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <8 x i8> %s0 to <8 x i32>
%s1s = zext <8 x i8> %s1 to <8 x i32>
@@ -117,16 +168,72 @@ entry:
ret <8 x i32> %m
}
+define <8 x i32> @extsubs_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1) {
+; CHECK-SD-LABEL: extsubs_v8i8_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ssubl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: sshll2 v1.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubs_v8i8_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: ssubl v0.4s, v2.4h, v1.4h
+; CHECK-GI-NEXT: ssubl2 v1.4s, v2.8h, v1.8h
+; CHECK-GI-NEXT: ret
+entry:
+ %s0s = sext <8 x i8> %s0 to <8 x i32>
+ %s1s = sext <8 x i8> %s1 to <8 x i32>
+ %m = sub <8 x i32> %s0s, %s1s
+ ret <8 x i32> %m
+}
+
+define <8 x i32> @extsubu_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1) {
+; CHECK-SD-LABEL: extsubu_v8i8_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: usubl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: sshll2 v1.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubu_v8i8_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: usubl v0.4s, v2.4h, v1.4h
+; CHECK-GI-NEXT: usubl2 v1.4s, v2.8h, v1.8h
+; CHECK-GI-NEXT: ret
+entry:
+ %s0s = zext <8 x i8> %s0 to <8 x i32>
+ %s1s = zext <8 x i8> %s1 to <8 x i32>
+ %m = sub <8 x i32> %s0s, %s1s
+ ret <8 x i32> %m
+}
+
define <16 x i32> @extadds_v16i8_i32(<16 x i8> %s0, <16 x i8> %s1) {
-; CHECK-LABEL: extadds_v16i8_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v2.8h, v0.8b, v1.8b
-; CHECK-NEXT: saddl2 v4.8h, v0.16b, v1.16b
-; CHECK-NEXT: sshll v0.4s, v2.4h, #0
-; CHECK-NEXT: sshll2 v3.4s, v4.8h, #0
-; CHECK-NEXT: sshll2 v1.4s, v2.8h, #0
-; CHECK-NEXT: sshll v2.4s, v4.4h, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extadds_v16i8_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: saddl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: saddl2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: sshll v0.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v3.4s, v4.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v2.4s, v4.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v16i8_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll2 v4.8h, v0.16b, #0
+; CHECK-GI-NEXT: sshll2 v5.8h, v1.16b, #0
+; CHECK-GI-NEXT: saddl v0.4s, v2.4h, v3.4h
+; CHECK-GI-NEXT: saddl2 v1.4s, v2.8h, v3.8h
+; CHECK-GI-NEXT: saddl v2.4s, v4.4h, v5.4h
+; CHECK-GI-NEXT: saddl2 v3.4s, v4.8h, v5.8h
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <16 x i8> %s0 to <16 x i32>
%s1s = sext <16 x i8> %s1 to <16 x i32>
@@ -135,15 +242,27 @@ entry:
}
define <16 x i32> @extaddu_v16i8_i32(<16 x i8> %s0, <16 x i8> %s1) {
-; CHECK-LABEL: extaddu_v16i8_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v2.8h, v0.8b, v1.8b
-; CHECK-NEXT: uaddl2 v4.8h, v0.16b, v1.16b
-; CHECK-NEXT: ushll v0.4s, v2.4h, #0
-; CHECK-NEXT: ushll2 v3.4s, v4.8h, #0
-; CHECK-NEXT: ushll2 v1.4s, v2.8h, #0
-; CHECK-NEXT: ushll v2.4s, v4.4h, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extaddu_v16i8_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: uaddl2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: ushll v0.4s, v2.4h, #0
+; CHECK-SD-NEXT: ushll2 v3.4s, v4.8h, #0
+; CHECK-SD-NEXT: ushll2 v1.4s, v2.8h, #0
+; CHECK-SD-NEXT: ushll v2.4s, v4.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v16i8_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: ushll2 v4.8h, v0.16b, #0
+; CHECK-GI-NEXT: ushll2 v5.8h, v1.16b, #0
+; CHECK-GI-NEXT: uaddl v0.4s, v2.4h, v3.4h
+; CHECK-GI-NEXT: uaddl2 v1.4s, v2.8h, v3.8h
+; CHECK-GI-NEXT: uaddl v2.4s, v4.4h, v5.4h
+; CHECK-GI-NEXT: uaddl2 v3.4s, v4.8h, v5.8h
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <16 x i8> %s0 to <16 x i32>
%s1s = zext <16 x i8> %s1 to <16 x i32>
@@ -151,17 +270,89 @@ entry:
ret <16 x i32> %m
}
+define <16 x i32> @extsubs_v16i8_i32(<16 x i8> %s0, <16 x i8> %s1) {
+; CHECK-SD-LABEL: extsubs_v16i8_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ssubl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: ssubl2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: sshll v0.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v3.4s, v4.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v2.4s, v4.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubs_v16i8_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll2 v4.8h, v0.16b, #0
+; CHECK-GI-NEXT: sshll2 v5.8h, v1.16b, #0
+; CHECK-GI-NEXT: ssubl v0.4s, v2.4h, v3.4h
+; CHECK-GI-NEXT: ssubl2 v1.4s, v2.8h, v3.8h
+; CHECK-GI-NEXT: ssubl v2.4s, v4.4h, v5.4h
+; CHECK-GI-NEXT: ssubl2 v3.4s, v4.8h, v5.8h
+; CHECK-GI-NEXT: ret
+entry:
+ %s0s = sext <16 x i8> %s0 to <16 x i32>
+ %s1s = sext <16 x i8> %s1 to <16 x i32>
+ %m = sub <16 x i32> %s0s, %s1s
+ ret <16 x i32> %m
+}
+
+define <16 x i32> @extsubu_v16i8_i32(<16 x i8> %s0, <16 x i8> %s1) {
+; CHECK-SD-LABEL: extsubu_v16i8_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: usubl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: usubl2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: sshll v0.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v3.4s, v4.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v2.4s, v4.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubu_v16i8_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: ushll2 v4.8h, v0.16b, #0
+; CHECK-GI-NEXT: ushll2 v5.8h, v1.16b, #0
+; CHECK-GI-NEXT: usubl v0.4s, v2.4h, v3.4h
+; CHECK-GI-NEXT: usubl2 v1.4s, v2.8h, v3.8h
+; CHECK-GI-NEXT: usubl v2.4s, v4.4h, v5.4h
+; CHECK-GI-NEXT: usubl2 v3.4s, v4.8h, v5.8h
+; CHECK-GI-NEXT: ret
+entry:
+ %s0s = zext <16 x i8> %s0 to <16 x i32>
+ %s1s = zext <16 x i8> %s1 to <16 x i32>
+ %m = sub <16 x i32> %s0s, %s1s
+ ret <16 x i32> %m
+}
+
define <8 x i64> @extadds_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1) {
-; CHECK-LABEL: extadds_v8i8_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: sshll v1.4s, v0.4h, #0
-; CHECK-NEXT: sshll2 v2.4s, v0.8h, #0
-; CHECK-NEXT: sshll v0.2d, v1.2s, #0
-; CHECK-NEXT: sshll2 v3.2d, v2.4s, #0
-; CHECK-NEXT: sshll2 v1.2d, v1.4s, #0
-; CHECK-NEXT: sshll v2.2d, v2.2s, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extadds_v8i8_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: saddl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll v0.2d, v1.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v1.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v8i8_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: saddl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: saddl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: saddl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: saddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <8 x i8> %s0 to <8 x i64>
%s1s = sext <8 x i8> %s1 to <8 x i64>
@@ -170,16 +361,30 @@ entry:
}
define <8 x i64> @extaddu_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1) {
-; CHECK-LABEL: extaddu_v8i8_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ushll v1.4s, v0.4h, #0
-; CHECK-NEXT: ushll2 v2.4s, v0.8h, #0
-; CHECK-NEXT: ushll v0.2d, v1.2s, #0
-; CHECK-NEXT: ushll2 v3.2d, v2.4s, #0
-; CHECK-NEXT: ushll2 v1.2d, v1.4s, #0
-; CHECK-NEXT: ushll v2.2d, v2.2s, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extaddu_v8i8_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: ushll v0.2d, v1.2s, #0
+; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: ushll2 v1.2d, v1.4s, #0
+; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v8i8_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: uaddl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: uaddl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: uaddl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: uaddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <8 x i8> %s0 to <8 x i64>
%s1s = zext <8 x i8> %s1 to <8 x i64>
@@ -187,6 +392,430 @@ entry:
ret <8 x i64> %m
}
+define <8 x i64> @extsubs_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1) {
+; CHECK-SD-LABEL: extsubs_v8i8_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ssubl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll v0.2d, v1.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v1.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubs_v8i8_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: ssubl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: ssubl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: ssubl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: ssubl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
+entry:
+ %s0s = sext <8 x i8> %s0 to <8 x i64>
+ %s1s = sext <8 x i8> %s1 to <8 x i64>
+ %m = sub <8 x i64> %s0s, %s1s
+ ret <8 x i64> %m
+}
+
+define <8 x i64> @extsubu_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1) {
+; CHECK-SD-LABEL: extsubu_v8i8_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: usubl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll v0.2d, v1.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v1.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubu_v8i8_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: usubl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: usubl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: usubl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: usubl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
+entry:
+ %s0s = zext <8 x i8> %s0 to <8 x i64>
+ %s1s = zext <8 x i8> %s1 to <8 x i64>
+ %m = sub <8 x i64> %s0s, %s1s
+ ret <8 x i64> %m
+}
+
+define <16 x i64> @extaddu_v16i8_i64(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: extaddu_v16i8_i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uaddl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: uaddl2 v0.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: ushll v3.4s, v2.4h, #0
+; CHECK-SD-NEXT: ushll2 v2.4s, v2.8h, #0
+; CHECK-SD-NEXT: ushll v5.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll2 v6.4s, v0.8h, #0
+; CHECK-SD-NEXT: ushll2 v1.2d, v3.4s, #0
+; CHECK-SD-NEXT: ushll v0.2d, v3.2s, #0
+; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: ushll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: ushll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: ushll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: ushll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v16i8_i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: ushll2 v1.8h, v1.16b, #0
+; CHECK-GI-NEXT: ushll v4.4s, v2.4h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v2.8h, #0
+; CHECK-GI-NEXT: ushll v2.4s, v3.4h, #0
+; CHECK-GI-NEXT: ushll v6.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v3.4s, v3.8h, #0
+; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v16.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll2 v17.4s, v1.8h, #0
+; CHECK-GI-NEXT: uaddl v0.2d, v4.2s, v2.2s
+; CHECK-GI-NEXT: uaddl2 v1.2d, v4.4s, v2.4s
+; CHECK-GI-NEXT: uaddl v2.2d, v5.2s, v3.2s
+; CHECK-GI-NEXT: uaddl2 v3.2d, v5.4s, v3.4s
+; CHECK-GI-NEXT: uaddl v4.2d, v6.2s, v7.2s
+; CHECK-GI-NEXT: uaddl2 v5.2d, v6.4s, v7.4s
+; CHECK-GI-NEXT: uaddl v6.2d, v16.2s, v17.2s
+; CHECK-GI-NEXT: uaddl2 v7.2d, v16.4s, v17.4s
+; CHECK-GI-NEXT: ret
+ %c = zext <16 x i8> %a to <16 x i64>
+ %d = zext <16 x i8> %b to <16 x i64>
+ %e = add <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
+define <16 x i64> @extadds_v16i8_i64(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: extadds_v16i8_i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: saddl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: saddl2 v0.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: sshll v3.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v5.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v6.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v3.4s, #0
+; CHECK-SD-NEXT: sshll v0.2d, v3.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: sshll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: sshll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: sshll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v16i8_i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: sshll2 v1.8h, v1.16b, #0
+; CHECK-GI-NEXT: sshll v4.4s, v2.4h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v2.8h, #0
+; CHECK-GI-NEXT: sshll v2.4s, v3.4h, #0
+; CHECK-GI-NEXT: sshll v6.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v3.4s, v3.8h, #0
+; CHECK-GI-NEXT: sshll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v16.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll2 v17.4s, v1.8h, #0
+; CHECK-GI-NEXT: saddl v0.2d, v4.2s, v2.2s
+; CHECK-GI-NEXT: saddl2 v1.2d, v4.4s, v2.4s
+; CHECK-GI-NEXT: saddl v2.2d, v5.2s, v3.2s
+; CHECK-GI-NEXT: saddl2 v3.2d, v5.4s, v3.4s
+; CHECK-GI-NEXT: saddl v4.2d, v6.2s, v7.2s
+; CHECK-GI-NEXT: saddl2 v5.2d, v6.4s, v7.4s
+; CHECK-GI-NEXT: saddl v6.2d, v16.2s, v17.2s
+; CHECK-GI-NEXT: saddl2 v7.2d, v16.4s, v17.4s
+; CHECK-GI-NEXT: ret
+ %c = sext <16 x i8> %a to <16 x i64>
+ %d = sext <16 x i8> %b to <16 x i64>
+ %e = add <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
+define <16 x i64> @extsubu_v16i8_i64(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: extsubu_v16i8_i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: usubl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: usubl2 v0.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: sshll v3.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v5.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v6.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v3.4s, #0
+; CHECK-SD-NEXT: sshll v0.2d, v3.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: sshll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: sshll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: sshll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubu_v16i8_i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: ushll2 v1.8h, v1.16b, #0
+; CHECK-GI-NEXT: ushll v4.4s, v2.4h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v2.8h, #0
+; CHECK-GI-NEXT: ushll v2.4s, v3.4h, #0
+; CHECK-GI-NEXT: ushll v6.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v3.4s, v3.8h, #0
+; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v16.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll2 v17.4s, v1.8h, #0
+; CHECK-GI-NEXT: usubl v0.2d, v4.2s, v2.2s
+; CHECK-GI-NEXT: usubl2 v1.2d, v4.4s, v2.4s
+; CHECK-GI-NEXT: usubl v2.2d, v5.2s, v3.2s
+; CHECK-GI-NEXT: usubl2 v3.2d, v5.4s, v3.4s
+; CHECK-GI-NEXT: usubl v4.2d, v6.2s, v7.2s
+; CHECK-GI-NEXT: usubl2 v5.2d, v6.4s, v7.4s
+; CHECK-GI-NEXT: usubl v6.2d, v16.2s, v17.2s
+; CHECK-GI-NEXT: usubl2 v7.2d, v16.4s, v17.4s
+; CHECK-GI-NEXT: ret
+ %c = zext <16 x i8> %a to <16 x i64>
+ %d = zext <16 x i8> %b to <16 x i64>
+ %e = sub <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
+define <16 x i64> @extsubs_v16i8_i64(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: extsubs_v16i8_i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ssubl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: ssubl2 v0.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: sshll v3.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v5.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v6.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v3.4s, #0
+; CHECK-SD-NEXT: sshll v0.2d, v3.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: sshll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: sshll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: sshll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubs_v16i8_i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: sshll2 v1.8h, v1.16b, #0
+; CHECK-GI-NEXT: sshll v4.4s, v2.4h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v2.8h, #0
+; CHECK-GI-NEXT: sshll v2.4s, v3.4h, #0
+; CHECK-GI-NEXT: sshll v6.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v3.4s, v3.8h, #0
+; CHECK-GI-NEXT: sshll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v16.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll2 v17.4s, v1.8h, #0
+; CHECK-GI-NEXT: ssubl v0.2d, v4.2s, v2.2s
+; CHECK-GI-NEXT: ssubl2 v1.2d, v4.4s, v2.4s
+; CHECK-GI-NEXT: ssubl v2.2d, v5.2s, v3.2s
+; CHECK-GI-NEXT: ssubl2 v3.2d, v5.4s, v3.4s
+; CHECK-GI-NEXT: ssubl v4.2d, v6.2s, v7.2s
+; CHECK-GI-NEXT: ssubl2 v5.2d, v6.4s, v7.4s
+; CHECK-GI-NEXT: ssubl v6.2d, v16.2s, v17.2s
+; CHECK-GI-NEXT: ssubl2 v7.2d, v16.4s, v17.4s
+; CHECK-GI-NEXT: ret
+ %c = sext <16 x i8> %a to <16 x i64>
+ %d = sext <16 x i8> %b to <16 x i64>
+ %e = sub <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
+define <16 x i64> @extaddu_v16i16_i64(<16 x i16> %a, <16 x i16> %b) {
+; CHECK-SD-LABEL: extaddu_v16i16_i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uaddl v5.4s, v1.4h, v3.4h
+; CHECK-SD-NEXT: uaddl v4.4s, v0.4h, v2.4h
+; CHECK-SD-NEXT: uaddl2 v2.4s, v0.8h, v2.8h
+; CHECK-SD-NEXT: uaddl2 v6.4s, v1.8h, v3.8h
+; CHECK-SD-NEXT: ushll2 v1.2d, v4.4s, #0
+; CHECK-SD-NEXT: ushll v0.2d, v4.2s, #0
+; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: ushll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: ushll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: ushll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: ushll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v16i16_i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v4.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll v6.4s, v2.4h, #0
+; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v16.4s, v2.8h, #0
+; CHECK-GI-NEXT: ushll v17.4s, v3.4h, #0
+; CHECK-GI-NEXT: ushll2 v18.4s, v1.8h, #0
+; CHECK-GI-NEXT: ushll2 v19.4s, v3.8h, #0
+; CHECK-GI-NEXT: uaddl v0.2d, v4.2s, v6.2s
+; CHECK-GI-NEXT: uaddl2 v1.2d, v4.4s, v6.4s
+; CHECK-GI-NEXT: uaddl v2.2d, v5.2s, v16.2s
+; CHECK-GI-NEXT: uaddl2 v3.2d, v5.4s, v16.4s
+; CHECK-GI-NEXT: uaddl v4.2d, v7.2s, v17.2s
+; CHECK-GI-NEXT: uaddl2 v5.2d, v7.4s, v17.4s
+; CHECK-GI-NEXT: uaddl v6.2d, v18.2s, v19.2s
+; CHECK-GI-NEXT: uaddl2 v7.2d, v18.4s, v19.4s
+; CHECK-GI-NEXT: ret
+ %c = zext <16 x i16> %a to <16 x i64>
+ %d = zext <16 x i16> %b to <16 x i64>
+ %e = add <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
+define <16 x i64> @extadds_v16i16_i64(<16 x i16> %a, <16 x i16> %b) {
+; CHECK-SD-LABEL: extadds_v16i16_i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: saddl v5.4s, v1.4h, v3.4h
+; CHECK-SD-NEXT: saddl v4.4s, v0.4h, v2.4h
+; CHECK-SD-NEXT: saddl2 v2.4s, v0.8h, v2.8h
+; CHECK-SD-NEXT: saddl2 v6.4s, v1.8h, v3.8h
+; CHECK-SD-NEXT: sshll2 v1.2d, v4.4s, #0
+; CHECK-SD-NEXT: sshll v0.2d, v4.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: sshll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: sshll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: sshll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v16i16_i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v4.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll v6.4s, v2.4h, #0
+; CHECK-GI-NEXT: sshll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v16.4s, v2.8h, #0
+; CHECK-GI-NEXT: sshll v17.4s, v3.4h, #0
+; CHECK-GI-NEXT: sshll2 v18.4s, v1.8h, #0
+; CHECK-GI-NEXT: sshll2 v19.4s, v3.8h, #0
+; CHECK-GI-NEXT: saddl v0.2d, v4.2s, v6.2s
+; CHECK-GI-NEXT: saddl2 v1.2d, v4.4s, v6.4s
+; CHECK-GI-NEXT: saddl v2.2d, v5.2s, v16.2s
+; CHECK-GI-NEXT: saddl2 v3.2d, v5.4s, v16.4s
+; CHECK-GI-NEXT: saddl v4.2d, v7.2s, v17.2s
+; CHECK-GI-NEXT: saddl2 v5.2d, v7.4s, v17.4s
+; CHECK-GI-NEXT: saddl v6.2d, v18.2s, v19.2s
+; CHECK-GI-NEXT: saddl2 v7.2d, v18.4s, v19.4s
+; CHECK-GI-NEXT: ret
+ %c = sext <16 x i16> %a to <16 x i64>
+ %d = sext <16 x i16> %b to <16 x i64>
+ %e = add <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
+define <16 x i64> @extsubu_v16i16_i64(<16 x i16> %a, <16 x i16> %b) {
+; CHECK-SD-LABEL: extsubu_v16i16_i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: usubl v5.4s, v1.4h, v3.4h
+; CHECK-SD-NEXT: usubl v4.4s, v0.4h, v2.4h
+; CHECK-SD-NEXT: usubl2 v2.4s, v0.8h, v2.8h
+; CHECK-SD-NEXT: usubl2 v6.4s, v1.8h, v3.8h
+; CHECK-SD-NEXT: sshll2 v1.2d, v4.4s, #0
+; CHECK-SD-NEXT: sshll v0.2d, v4.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: sshll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: sshll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: sshll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubu_v16i16_i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v4.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll v6.4s, v2.4h, #0
+; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v16.4s, v2.8h, #0
+; CHECK-GI-NEXT: ushll v17.4s, v3.4h, #0
+; CHECK-GI-NEXT: ushll2 v18.4s, v1.8h, #0
+; CHECK-GI-NEXT: ushll2 v19.4s, v3.8h, #0
+; CHECK-GI-NEXT: usubl v0.2d, v4.2s, v6.2s
+; CHECK-GI-NEXT: usubl2 v1.2d, v4.4s, v6.4s
+; CHECK-GI-NEXT: usubl v2.2d, v5.2s, v16.2s
+; CHECK-GI-NEXT: usubl2 v3.2d, v5.4s, v16.4s
+; CHECK-GI-NEXT: usubl v4.2d, v7.2s, v17.2s
+; CHECK-GI-NEXT: usubl2 v5.2d, v7.4s, v17.4s
+; CHECK-GI-NEXT: usubl v6.2d, v18.2s, v19.2s
+; CHECK-GI-NEXT: usubl2 v7.2d, v18.4s, v19.4s
+; CHECK-GI-NEXT: ret
+ %c = zext <16 x i16> %a to <16 x i64>
+ %d = zext <16 x i16> %b to <16 x i64>
+ %e = sub <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
+define <16 x i64> @extsubs_v16i16_i64(<16 x i16> %a, <16 x i16> %b) {
+; CHECK-SD-LABEL: extsubs_v16i16_i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ssubl v5.4s, v1.4h, v3.4h
+; CHECK-SD-NEXT: ssubl v4.4s, v0.4h, v2.4h
+; CHECK-SD-NEXT: ssubl2 v2.4s, v0.8h, v2.8h
+; CHECK-SD-NEXT: ssubl2 v6.4s, v1.8h, v3.8h
+; CHECK-SD-NEXT: sshll2 v1.2d, v4.4s, #0
+; CHECK-SD-NEXT: sshll v0.2d, v4.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: sshll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: sshll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: sshll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubs_v16i16_i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v4.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll v6.4s, v2.4h, #0
+; CHECK-GI-NEXT: sshll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v16.4s, v2.8h, #0
+; CHECK-GI-NEXT: sshll v17.4s, v3.4h, #0
+; CHECK-GI-NEXT: sshll2 v18.4s, v1.8h, #0
+; CHECK-GI-NEXT: sshll2 v19.4s, v3.8h, #0
+; CHECK-GI-NEXT: ssubl v0.2d, v4.2s, v6.2s
+; CHECK-GI-NEXT: ssubl2 v1.2d, v4.4s, v6.4s
+; CHECK-GI-NEXT: ssubl v2.2d, v5.2s, v16.2s
+; CHECK-GI-NEXT: ssubl2 v3.2d, v5.4s, v16.4s
+; CHECK-GI-NEXT: ssubl v4.2d, v7.2s, v17.2s
+; CHECK-GI-NEXT: ssubl2 v5.2d, v7.4s, v17.4s
+; CHECK-GI-NEXT: ssubl v6.2d, v18.2s, v19.2s
+; CHECK-GI-NEXT: ssubl2 v7.2d, v18.4s, v19.4s
+; CHECK-GI-NEXT: ret
+ %c = sext <16 x i16> %a to <16 x i64>
+ %d = sext <16 x i16> %b to <16 x i64>
+ %e = sub <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
define <4 x i32> @extadds_v4i16_i32(<4 x i16> %s0, <4 x i16> %s1) {
; CHECK-LABEL: extadds_v4i16_i32:
; CHECK: // %bb.0: // %entry
@@ -212,12 +841,19 @@ entry:
}
define <8 x i32> @extadds_v8i16_i32(<8 x i16> %s0, <8 x i16> %s1) {
-; CHECK-LABEL: extadds_v8i16_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl2 v2.4s, v0.8h, v1.8h
-; CHECK-NEXT: saddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: mov v1.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extadds_v8i16_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: saddl2 v2.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: saddl v0.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v8i16_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: saddl v2.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: saddl2 v1.4s, v0.8h, v1.8h
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <8 x i16> %s0 to <8 x i32>
%s1s = sext <8 x i16> %s1 to <8 x i32>
@@ -226,12 +862,19 @@ entry:
}
define <8 x i32> @extaddu_v8i16_i32(<8 x i16> %s0, <8 x i16> %s1) {
-; CHECK-LABEL: extaddu_v8i16_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl2 v2.4s, v0.8h, v1.8h
-; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: mov v1.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extaddu_v8i16_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddl2 v2.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: uaddl v0.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v8i16_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: uaddl v2.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: uaddl2 v1.4s, v0.8h, v1.8h
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <8 x i16> %s0 to <8 x i32>
%s1s = zext <8 x i16> %s1 to <8 x i32>
@@ -240,16 +883,26 @@ entry:
}
define <16 x i32> @extadds_v16i16_i32(<16 x i16> %s0, <16 x i16> %s1) {
-; CHECK-LABEL: extadds_v16i16_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl2 v4.4s, v1.8h, v3.8h
-; CHECK-NEXT: saddl v5.4s, v0.4h, v2.4h
-; CHECK-NEXT: saddl2 v6.4s, v0.8h, v2.8h
-; CHECK-NEXT: saddl v2.4s, v1.4h, v3.4h
-; CHECK-NEXT: mov v0.16b, v5.16b
-; CHECK-NEXT: mov v1.16b, v6.16b
-; CHECK-NEXT: mov v3.16b, v4.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extadds_v16i16_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: saddl2 v4.4s, v1.8h, v3.8h
+; CHECK-SD-NEXT: saddl v5.4s, v0.4h, v2.4h
+; CHECK-SD-NEXT: saddl2 v6.4s, v0.8h, v2.8h
+; CHECK-SD-NEXT: saddl v2.4s, v1.4h, v3.4h
+; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: mov v1.16b, v6.16b
+; CHECK-SD-NEXT: mov v3.16b, v4.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v16i16_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: saddl v4.4s, v0.4h, v2.4h
+; CHECK-GI-NEXT: saddl2 v5.4s, v0.8h, v2.8h
+; CHECK-GI-NEXT: saddl v2.4s, v1.4h, v3.4h
+; CHECK-GI-NEXT: saddl2 v3.4s, v1.8h, v3.8h
+; CHECK-GI-NEXT: mov v0.16b, v4.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <16 x i16> %s0 to <16 x i32>
%s1s = sext <16 x i16> %s1 to <16 x i32>
@@ -258,16 +911,26 @@ entry:
}
define <16 x i32> @extaddu_v16i16_i32(<16 x i16> %s0, <16 x i16> %s1) {
-; CHECK-LABEL: extaddu_v16i16_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl2 v4.4s, v1.8h, v3.8h
-; CHECK-NEXT: uaddl v5.4s, v0.4h, v2.4h
-; CHECK-NEXT: uaddl2 v6.4s, v0.8h, v2.8h
-; CHECK-NEXT: uaddl v2.4s, v1.4h, v3.4h
-; CHECK-NEXT: mov v0.16b, v5.16b
-; CHECK-NEXT: mov v1.16b, v6.16b
-; CHECK-NEXT: mov v3.16b, v4.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extaddu_v16i16_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddl2 v4.4s, v1.8h, v3.8h
+; CHECK-SD-NEXT: uaddl v5.4s, v0.4h, v2.4h
+; CHECK-SD-NEXT: uaddl2 v6.4s, v0.8h, v2.8h
+; CHECK-SD-NEXT: uaddl v2.4s, v1.4h, v3.4h
+; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: mov v1.16b, v6.16b
+; CHECK-SD-NEXT: mov v3.16b, v4.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v16i16_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: uaddl v4.4s, v0.4h, v2.4h
+; CHECK-GI-NEXT: uaddl2 v5.4s, v0.8h, v2.8h
+; CHECK-GI-NEXT: uaddl v2.4s, v1.4h, v3.4h
+; CHECK-GI-NEXT: uaddl2 v3.4s, v1.8h, v3.8h
+; CHECK-GI-NEXT: mov v0.16b, v4.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <16 x i16> %s0 to <16 x i32>
%s1s = zext <16 x i16> %s1 to <16 x i32>
@@ -276,12 +939,20 @@ entry:
}
define <4 x i64> @extadds_v4i16_i64(<4 x i16> %s0, <4 x i16> %s1) {
-; CHECK-LABEL: extadds_v4i16_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: sshll2 v1.2d, v0.4s, #0
-; CHECK-NEXT: sshll v0.2d, v0.2s, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extadds_v4i16_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: saddl v0.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: sshll2 v1.2d, v0.4s, #0
+; CHECK-SD-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v4i16_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll v1.4s, v1.4h, #0
+; CHECK-GI-NEXT: saddl v0.2d, v2.2s, v1.2s
+; CHECK-GI-NEXT: saddl2 v1.2d, v2.4s, v1.4s
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <4 x i16> %s0 to <4 x i64>
%s1s = sext <4 x i16> %s1 to <4 x i64>
@@ -290,12 +961,20 @@ entry:
}
define <4 x i64> @extaddu_v4i16_i64(<4 x i16> %s0, <4 x i16> %s1) {
-; CHECK-LABEL: extaddu_v4i16_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: ushll2 v1.2d, v0.4s, #0
-; CHECK-NEXT: ushll v0.2d, v0.2s, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extaddu_v4i16_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddl v0.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: ushll2 v1.2d, v0.4s, #0
+; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v4i16_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-GI-NEXT: uaddl v0.2d, v2.2s, v1.2s
+; CHECK-GI-NEXT: uaddl2 v1.2d, v2.4s, v1.4s
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <4 x i16> %s0 to <4 x i64>
%s1s = zext <4 x i16> %s1 to <4 x i64>
@@ -304,15 +983,27 @@ entry:
}
define <8 x i64> @extadds_v8i16_i64(<8 x i16> %s0, <8 x i16> %s1) {
-; CHECK-LABEL: extadds_v8i16_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v2.4s, v0.4h, v1.4h
-; CHECK-NEXT: saddl2 v4.4s, v0.8h, v1.8h
-; CHECK-NEXT: sshll v0.2d, v2.2s, #0
-; CHECK-NEXT: sshll2 v3.2d, v4.4s, #0
-; CHECK-NEXT: sshll2 v1.2d, v2.4s, #0
-; CHECK-NEXT: sshll v2.2d, v4.2s, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extadds_v8i16_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: saddl v2.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: saddl2 v4.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: sshll v0.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v4.4s, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v4.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v8i16_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: saddl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: saddl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: saddl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: saddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <8 x i16> %s0 to <8 x i64>
%s1s = sext <8 x i16> %s1 to <8 x i64>
@@ -321,15 +1012,27 @@ entry:
}
define <8 x i64> @extaddu_v8i16_i64(<8 x i16> %s0, <8 x i16> %s1) {
-; CHECK-LABEL: extaddu_v8i16_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v2.4s, v0.4h, v1.4h
-; CHECK-NEXT: uaddl2 v4.4s, v0.8h, v1.8h
-; CHECK-NEXT: ushll v0.2d, v2.2s, #0
-; CHECK-NEXT: ushll2 v3.2d, v4.4s, #0
-; CHECK-NEXT: ushll2 v1.2d, v2.4s, #0
-; CHECK-NEXT: ushll v2.2d, v4.2s, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extaddu_v8i16_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddl v2.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: uaddl2 v4.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: ushll v0.2d, v2.2s, #0
+; CHECK-SD-NEXT: ushll2 v3.2d, v4.4s, #0
+; CHECK-SD-NEXT: ushll2 v1.2d, v2.4s, #0
+; CHECK-SD-NEXT: ushll v2.2d, v4.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v8i16_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: uaddl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: uaddl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: uaddl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: uaddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <8 x i16> %s0 to <8 x i64>
%s1s = zext <8 x i16> %s1 to <8 x i64>
@@ -337,6 +1040,64 @@ entry:
ret <8 x i64> %m
}
+define <8 x i64> @extsubs_v8i16_i64(<8 x i16> %s0, <8 x i16> %s1) {
+; CHECK-SD-LABEL: extsubs_v8i16_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ssubl v2.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: ssubl2 v4.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: sshll v0.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v4.4s, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v4.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubs_v8i16_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: ssubl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: ssubl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: ssubl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: ssubl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
+entry:
+ %s0s = sext <8 x i16> %s0 to <8 x i64>
+ %s1s = sext <8 x i16> %s1 to <8 x i64>
+ %m = sub <8 x i64> %s0s, %s1s
+ ret <8 x i64> %m
+}
+
+define <8 x i64> @extsubu_v8i16_i64(<8 x i16> %s0, <8 x i16> %s1) {
+; CHECK-SD-LABEL: extsubu_v8i16_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: usubl v2.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: usubl2 v4.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: sshll v0.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v4.4s, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v4.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extsubu_v8i16_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: usubl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: usubl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: usubl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: usubl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
+entry:
+ %s0s = zext <8 x i16> %s0 to <8 x i64>
+ %s1s = zext <8 x i16> %s1 to <8 x i64>
+ %m = sub <8 x i64> %s0s, %s1s
+ ret <8 x i64> %m
+}
+
define <2 x i64> @extadds_v2i32_i64(<2 x i32> %s0, <2 x i32> %s1) {
; CHECK-LABEL: extadds_v2i32_i64:
; CHECK: // %bb.0: // %entry
@@ -362,12 +1123,19 @@ entry:
}
define <4 x i64> @extadds_v4i32_i64(<4 x i32> %s0, <4 x i32> %s1) {
-; CHECK-LABEL: extadds_v4i32_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl2 v2.2d, v0.4s, v1.4s
-; CHECK-NEXT: saddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: mov v1.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extadds_v4i32_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: saddl2 v2.2d, v0.4s, v1.4s
+; CHECK-SD-NEXT: saddl v0.2d, v0.2s, v1.2s
+; CHECK-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v4i32_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: saddl v2.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: saddl2 v1.2d, v0.4s, v1.4s
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <4 x i32> %s0 to <4 x i64>
%s1s = sext <4 x i32> %s1 to <4 x i64>
@@ -376,12 +1144,19 @@ entry:
}
define <4 x i64> @extaddu_v4i32_i64(<4 x i32> %s0, <4 x i32> %s1) {
-; CHECK-LABEL: extaddu_v4i32_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl2 v2.2d, v0.4s, v1.4s
-; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: mov v1.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extaddu_v4i32_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddl2 v2.2d, v0.4s, v1.4s
+; CHECK-SD-NEXT: uaddl v0.2d, v0.2s, v1.2s
+; CHECK-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v4i32_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: uaddl v2.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: uaddl2 v1.2d, v0.4s, v1.4s
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <4 x i32> %s0 to <4 x i64>
%s1s = zext <4 x i32> %s1 to <4 x i64>
@@ -390,16 +1165,26 @@ entry:
}
define <8 x i64> @extadds_v8i32_i64(<8 x i32> %s0, <8 x i32> %s1) {
-; CHECK-LABEL: extadds_v8i32_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl2 v4.2d, v1.4s, v3.4s
-; CHECK-NEXT: saddl v5.2d, v0.2s, v2.2s
-; CHECK-NEXT: saddl2 v6.2d, v0.4s, v2.4s
-; CHECK-NEXT: saddl v2.2d, v1.2s, v3.2s
-; CHECK-NEXT: mov v0.16b, v5.16b
-; CHECK-NEXT: mov v1.16b, v6.16b
-; CHECK-NEXT: mov v3.16b, v4.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extadds_v8i32_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: saddl2 v4.2d, v1.4s, v3.4s
+; CHECK-SD-NEXT: saddl v5.2d, v0.2s, v2.2s
+; CHECK-SD-NEXT: saddl2 v6.2d, v0.4s, v2.4s
+; CHECK-SD-NEXT: saddl v2.2d, v1.2s, v3.2s
+; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: mov v1.16b, v6.16b
+; CHECK-SD-NEXT: mov v3.16b, v4.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extadds_v8i32_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: saddl v4.2d, v0.2s, v2.2s
+; CHECK-GI-NEXT: saddl2 v5.2d, v0.4s, v2.4s
+; CHECK-GI-NEXT: saddl v2.2d, v1.2s, v3.2s
+; CHECK-GI-NEXT: saddl2 v3.2d, v1.4s, v3.4s
+; CHECK-GI-NEXT: mov v0.16b, v4.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <8 x i32> %s0 to <8 x i64>
%s1s = sext <8 x i32> %s1 to <8 x i64>
@@ -408,16 +1193,26 @@ entry:
}
define <8 x i64> @extaddu_v8i32_i64(<8 x i32> %s0, <8 x i32> %s1) {
-; CHECK-LABEL: extaddu_v8i32_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl2 v4.2d, v1.4s, v3.4s
-; CHECK-NEXT: uaddl v5.2d, v0.2s, v2.2s
-; CHECK-NEXT: uaddl2 v6.2d, v0.4s, v2.4s
-; CHECK-NEXT: uaddl v2.2d, v1.2s, v3.2s
-; CHECK-NEXT: mov v0.16b, v5.16b
-; CHECK-NEXT: mov v1.16b, v6.16b
-; CHECK-NEXT: mov v3.16b, v4.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extaddu_v8i32_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddl2 v4.2d, v1.4s, v3.4s
+; CHECK-SD-NEXT: uaddl v5.2d, v0.2s, v2.2s
+; CHECK-SD-NEXT: uaddl2 v6.2d, v0.4s, v2.4s
+; CHECK-SD-NEXT: uaddl v2.2d, v1.2s, v3.2s
+; CHECK-SD-NEXT: mov v0.16b, v5.16b
+; CHECK-SD-NEXT: mov v1.16b, v6.16b
+; CHECK-SD-NEXT: mov v3.16b, v4.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extaddu_v8i32_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: uaddl v4.2d, v0.2s, v2.2s
+; CHECK-GI-NEXT: uaddl2 v5.2d, v0.4s, v2.4s
+; CHECK-GI-NEXT: uaddl v2.2d, v1.2s, v3.2s
+; CHECK-GI-NEXT: uaddl2 v3.2d, v1.4s, v3.4s
+; CHECK-GI-NEXT: mov v0.16b, v4.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <8 x i32> %s0 to <8 x i64>
%s1s = zext <8 x i32> %s1 to <8 x i64>
@@ -426,17 +1221,33 @@ entry:
}
define <16 x i32> @add_zs(<16 x i8> %s0, <16 x i8> %s1) {
-; CHECK-LABEL: add_zs:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ushll v2.8h, v0.8b, #0
-; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0
-; CHECK-NEXT: saddw v2.8h, v2.8h, v1.8b
-; CHECK-NEXT: saddw2 v4.8h, v0.8h, v1.16b
-; CHECK-NEXT: sshll v0.4s, v2.4h, #0
-; CHECK-NEXT: sshll2 v3.4s, v4.8h, #0
-; CHECK-NEXT: sshll2 v1.4s, v2.8h, #0
-; CHECK-NEXT: sshll v2.4s, v4.4h, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: add_zs:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-SD-NEXT: saddw v2.8h, v2.8h, v1.8b
+; CHECK-SD-NEXT: saddw2 v4.8h, v0.8h, v1.16b
+; CHECK-SD-NEXT: sshll v0.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v3.4s, v4.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v2.4s, v4.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: add_zs:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll2 v1.8h, v1.16b, #0
+; CHECK-GI-NEXT: ushll v3.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll2 v4.8h, v0.16b, #0
+; CHECK-GI-NEXT: sshll v0.4s, v2.4h, #0
+; CHECK-GI-NEXT: sshll2 v2.4s, v2.8h, #0
+; CHECK-GI-NEXT: sshll v5.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v6.4s, v1.8h, #0
+; CHECK-GI-NEXT: uaddw v0.4s, v0.4s, v3.4h
+; CHECK-GI-NEXT: uaddw2 v1.4s, v2.4s, v3.8h
+; CHECK-GI-NEXT: uaddw v2.4s, v5.4s, v4.4h
+; CHECK-GI-NEXT: uaddw2 v3.4s, v6.4s, v4.8h
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <16 x i8> %s0 to <16 x i32>
%s1s = sext <16 x i8> %s1 to <16 x i32>
@@ -445,87 +1256,174 @@ entry:
}
define <20 x i32> @v20(<20 x i8> %s0, <20 x i8> %s1) {
-; CHECK-LABEL: v20:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: ldr b2, [sp, #160]
-; CHECK-NEXT: add x10, sp, #168
-; CHECK-NEXT: ldr b3, [sp]
-; CHECK-NEXT: add x11, sp, #8
-; CHECK-NEXT: ldr b1, [sp, #96]
-; CHECK-NEXT: ld1 { v2.b }[1], [x10]
-; CHECK-NEXT: add x9, sp, #104
-; CHECK-NEXT: add x10, sp, #176
-; CHECK-NEXT: mov v0.b[1], w1
-; CHECK-NEXT: ld1 { v3.b }[1], [x11]
-; CHECK-NEXT: ld1 { v1.b }[1], [x9]
-; CHECK-NEXT: add x11, sp, #16
-; CHECK-NEXT: add x9, sp, #112
-; CHECK-NEXT: add x13, sp, #184
-; CHECK-NEXT: ld1 { v2.b }[2], [x10]
-; CHECK-NEXT: add x12, sp, #120
-; CHECK-NEXT: add x14, sp, #32
-; CHECK-NEXT: ld1 { v3.b }[2], [x11]
-; CHECK-NEXT: ld1 { v1.b }[2], [x9]
-; CHECK-NEXT: ldr b5, [sp, #64]
-; CHECK-NEXT: mov v0.b[2], w2
-; CHECK-NEXT: ldr b4, [sp, #224]
-; CHECK-NEXT: add x11, sp, #128
-; CHECK-NEXT: ld1 { v2.b }[3], [x13]
-; CHECK-NEXT: add x13, sp, #24
-; CHECK-NEXT: add x10, sp, #136
-; CHECK-NEXT: ld1 { v3.b }[3], [x13]
-; CHECK-NEXT: ld1 { v1.b }[3], [x12]
-; CHECK-NEXT: add x12, sp, #192
-; CHECK-NEXT: add x13, sp, #200
-; CHECK-NEXT: add x15, sp, #80
-; CHECK-NEXT: add x9, sp, #144
-; CHECK-NEXT: mov v0.b[3], w3
-; CHECK-NEXT: ld1 { v2.b }[4], [x12]
-; CHECK-NEXT: add x12, sp, #232
-; CHECK-NEXT: ld1 { v3.b }[4], [x14]
-; CHECK-NEXT: add x14, sp, #72
-; CHECK-NEXT: ld1 { v4.b }[1], [x12]
-; CHECK-NEXT: ld1 { v5.b }[1], [x14]
-; CHECK-NEXT: add x14, sp, #40
-; CHECK-NEXT: ld1 { v1.b }[4], [x11]
-; CHECK-NEXT: ld1 { v2.b }[5], [x13]
-; CHECK-NEXT: add x12, sp, #208
-; CHECK-NEXT: add x13, sp, #48
-; CHECK-NEXT: mov v0.b[4], w4
-; CHECK-NEXT: ld1 { v3.b }[5], [x14]
-; CHECK-NEXT: add x14, sp, #240
-; CHECK-NEXT: ld1 { v4.b }[2], [x14]
-; CHECK-NEXT: ld1 { v5.b }[2], [x15]
-; CHECK-NEXT: ld1 { v1.b }[5], [x10]
-; CHECK-NEXT: ld1 { v2.b }[6], [x12]
-; CHECK-NEXT: add x11, sp, #216
-; CHECK-NEXT: add x10, sp, #56
-; CHECK-NEXT: ld1 { v3.b }[6], [x13]
-; CHECK-NEXT: add x12, sp, #248
-; CHECK-NEXT: add x13, sp, #88
-; CHECK-NEXT: mov v0.b[5], w5
-; CHECK-NEXT: ld1 { v4.b }[3], [x12]
-; CHECK-NEXT: ld1 { v5.b }[3], [x13]
-; CHECK-NEXT: ld1 { v1.b }[6], [x9]
-; CHECK-NEXT: ld1 { v2.b }[7], [x11]
-; CHECK-NEXT: add x9, sp, #152
-; CHECK-NEXT: ld1 { v3.b }[7], [x10]
-; CHECK-NEXT: uaddl v4.8h, v5.8b, v4.8b
-; CHECK-NEXT: mov v0.b[6], w6
-; CHECK-NEXT: ld1 { v1.b }[7], [x9]
-; CHECK-NEXT: uaddl v2.8h, v3.8b, v2.8b
-; CHECK-NEXT: ushll v3.4s, v4.4h, #0
-; CHECK-NEXT: mov v0.b[7], w7
-; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ushll2 v1.4s, v2.8h, #0
-; CHECK-NEXT: ushll v2.4s, v2.4h, #0
-; CHECK-NEXT: stp q1, q3, [x8, #48]
-; CHECK-NEXT: ushll2 v3.4s, v0.8h, #0
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: stp q3, q2, [x8, #16]
-; CHECK-NEXT: str q0, [x8]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: v20:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fmov s0, w0
+; CHECK-SD-NEXT: ldr b2, [sp, #160]
+; CHECK-SD-NEXT: add x10, sp, #168
+; CHECK-SD-NEXT: ldr b3, [sp]
+; CHECK-SD-NEXT: add x11, sp, #8
+; CHECK-SD-NEXT: ldr b1, [sp, #96]
+; CHECK-SD-NEXT: ld1 { v2.b }[1], [x10]
+; CHECK-SD-NEXT: add x9, sp, #104
+; CHECK-SD-NEXT: add x10, sp, #176
+; CHECK-SD-NEXT: mov v0.b[1], w1
+; CHECK-SD-NEXT: ld1 { v3.b }[1], [x11]
+; CHECK-SD-NEXT: ld1 { v1.b }[1], [x9]
+; CHECK-SD-NEXT: add x11, sp, #16
+; CHECK-SD-NEXT: add x9, sp, #112
+; CHECK-SD-NEXT: add x13, sp, #184
+; CHECK-SD-NEXT: ld1 { v2.b }[2], [x10]
+; CHECK-SD-NEXT: add x12, sp, #120
+; CHECK-SD-NEXT: add x14, sp, #32
+; CHECK-SD-NEXT: ld1 { v3.b }[2], [x11]
+; CHECK-SD-NEXT: ld1 { v1.b }[2], [x9]
+; CHECK-SD-NEXT: ldr b5, [sp, #64]
+; CHECK-SD-NEXT: mov v0.b[2], w2
+; CHECK-SD-NEXT: ldr b4, [sp, #224]
+; CHECK-SD-NEXT: add x11, sp, #128
+; CHECK-SD-NEXT: ld1 { v2.b }[3], [x13]
+; CHECK-SD-NEXT: add x13, sp, #24
+; CHECK-SD-NEXT: add x10, sp, #136
+; CHECK-SD-NEXT: ld1 { v3.b }[3], [x13]
+; CHECK-SD-NEXT: ld1 { v1.b }[3], [x12]
+; CHECK-SD-NEXT: add x12, sp, #192
+; CHECK-SD-NEXT: add x13, sp, #200
+; CHECK-SD-NEXT: add x15, sp, #80
+; CHECK-SD-NEXT: add x9, sp, #144
+; CHECK-SD-NEXT: mov v0.b[3], w3
+; CHECK-SD-NEXT: ld1 { v2.b }[4], [x12]
+; CHECK-SD-NEXT: add x12, sp, #232
+; CHECK-SD-NEXT: ld1 { v3.b }[4], [x14]
+; CHECK-SD-NEXT: add x14, sp, #72
+; CHECK-SD-NEXT: ld1 { v4.b }[1], [x12]
+; CHECK-SD-NEXT: ld1 { v5.b }[1], [x14]
+; CHECK-SD-NEXT: add x14, sp, #40
+; CHECK-SD-NEXT: ld1 { v1.b }[4], [x11]
+; CHECK-SD-NEXT: ld1 { v2.b }[5], [x13]
+; CHECK-SD-NEXT: add x12, sp, #208
+; CHECK-SD-NEXT: add x13, sp, #48
+; CHECK-SD-NEXT: mov v0.b[4], w4
+; CHECK-SD-NEXT: ld1 { v3.b }[5], [x14]
+; CHECK-SD-NEXT: add x14, sp, #240
+; CHECK-SD-NEXT: ld1 { v4.b }[2], [x14]
+; CHECK-SD-NEXT: ld1 { v5.b }[2], [x15]
+; CHECK-SD-NEXT: ld1 { v1.b }[5], [x10]
+; CHECK-SD-NEXT: ld1 { v2.b }[6], [x12]
+; CHECK-SD-NEXT: add x11, sp, #216
+; CHECK-SD-NEXT: add x10, sp, #56
+; CHECK-SD-NEXT: ld1 { v3.b }[6], [x13]
+; CHECK-SD-NEXT: add x12, sp, #248
+; CHECK-SD-NEXT: add x13, sp, #88
+; CHECK-SD-NEXT: mov v0.b[5], w5
+; CHECK-SD-NEXT: ld1 { v4.b }[3], [x12]
+; CHECK-SD-NEXT: ld1 { v5.b }[3], [x13]
+; CHECK-SD-NEXT: ld1 { v1.b }[6], [x9]
+; CHECK-SD-NEXT: ld1 { v2.b }[7], [x11]
+; CHECK-SD-NEXT: add x9, sp, #152
+; CHECK-SD-NEXT: ld1 { v3.b }[7], [x10]
+; CHECK-SD-NEXT: uaddl v4.8h, v5.8b, v4.8b
+; CHECK-SD-NEXT: mov v0.b[6], w6
+; CHECK-SD-NEXT: ld1 { v1.b }[7], [x9]
+; CHECK-SD-NEXT: uaddl v2.8h, v3.8b, v2.8b
+; CHECK-SD-NEXT: ushll v3.4s, v4.4h, #0
+; CHECK-SD-NEXT: mov v0.b[7], w7
+; CHECK-SD-NEXT: uaddl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: ushll2 v1.4s, v2.8h, #0
+; CHECK-SD-NEXT: ushll v2.4s, v2.4h, #0
+; CHECK-SD-NEXT: stp q1, q3, [x8, #48]
+; CHECK-SD-NEXT: ushll2 v3.4s, v0.8h, #0
+; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: stp q3, q2, [x8, #16]
+; CHECK-SD-NEXT: str q0, [x8]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: v20:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldr s0, [sp]
+; CHECK-GI-NEXT: ldr s4, [sp, #8]
+; CHECK-GI-NEXT: fmov s1, w0
+; CHECK-GI-NEXT: ldr s18, [sp, #16]
+; CHECK-GI-NEXT: ldr s2, [sp, #32]
+; CHECK-GI-NEXT: fmov s3, w4
+; CHECK-GI-NEXT: mov v0.s[1], v4.s[0]
+; CHECK-GI-NEXT: ldr s16, [sp, #40]
+; CHECK-GI-NEXT: ldr s4, [sp, #64]
+; CHECK-GI-NEXT: ldr s19, [sp, #72]
+; CHECK-GI-NEXT: ldr s21, [sp, #104]
+; CHECK-GI-NEXT: mov v1.s[1], w1
+; CHECK-GI-NEXT: mov v2.s[1], v16.s[0]
+; CHECK-GI-NEXT: ldr s16, [sp, #96]
+; CHECK-GI-NEXT: ldr s22, [sp, #136]
+; CHECK-GI-NEXT: mov v3.s[1], w5
+; CHECK-GI-NEXT: ldr s20, [sp, #48]
+; CHECK-GI-NEXT: mov v4.s[1], v19.s[0]
+; CHECK-GI-NEXT: mov v0.s[2], v18.s[0]
+; CHECK-GI-NEXT: ldr s18, [sp, #128]
+; CHECK-GI-NEXT: ldr s19, [sp, #160]
+; CHECK-GI-NEXT: ldr s24, [sp, #168]
+; CHECK-GI-NEXT: mov v16.s[1], v21.s[0]
+; CHECK-GI-NEXT: ldr s21, [sp, #192]
+; CHECK-GI-NEXT: mov v18.s[1], v22.s[0]
+; CHECK-GI-NEXT: ldr s25, [sp, #200]
+; CHECK-GI-NEXT: ldr s22, [sp, #224]
+; CHECK-GI-NEXT: ldr s26, [sp, #232]
+; CHECK-GI-NEXT: ldr s23, [sp, #112]
+; CHECK-GI-NEXT: mov v19.s[1], v24.s[0]
+; CHECK-GI-NEXT: mov v2.s[2], v20.s[0]
+; CHECK-GI-NEXT: ldr s20, [sp, #144]
+; CHECK-GI-NEXT: ldr s17, [sp, #80]
+; CHECK-GI-NEXT: mov v21.s[1], v25.s[0]
+; CHECK-GI-NEXT: mov v22.s[1], v26.s[0]
+; CHECK-GI-NEXT: mov v1.s[2], w2
+; CHECK-GI-NEXT: mov v3.s[2], w6
+; CHECK-GI-NEXT: ldr s24, [sp, #176]
+; CHECK-GI-NEXT: mov v16.s[2], v23.s[0]
+; CHECK-GI-NEXT: mov v18.s[2], v20.s[0]
+; CHECK-GI-NEXT: mov v4.s[2], v17.s[0]
+; CHECK-GI-NEXT: ldr s17, [sp, #208]
+; CHECK-GI-NEXT: ldr s23, [sp, #240]
+; CHECK-GI-NEXT: ldr s20, [sp, #120]
+; CHECK-GI-NEXT: mov v19.s[2], v24.s[0]
+; CHECK-GI-NEXT: ldr s24, [sp, #152]
+; CHECK-GI-NEXT: ldr s5, [sp, #24]
+; CHECK-GI-NEXT: mov v21.s[2], v17.s[0]
+; CHECK-GI-NEXT: mov v22.s[2], v23.s[0]
+; CHECK-GI-NEXT: mov v1.s[3], w3
+; CHECK-GI-NEXT: mov v16.s[3], v20.s[0]
+; CHECK-GI-NEXT: movi v17.2d, #0x0000ff000000ff
+; CHECK-GI-NEXT: mov v3.s[3], w7
+; CHECK-GI-NEXT: mov v18.s[3], v24.s[0]
+; CHECK-GI-NEXT: ldr s6, [sp, #56]
+; CHECK-GI-NEXT: ldr s7, [sp, #88]
+; CHECK-GI-NEXT: ldr s25, [sp, #184]
+; CHECK-GI-NEXT: ldr s20, [sp, #216]
+; CHECK-GI-NEXT: mov v0.s[3], v5.s[0]
+; CHECK-GI-NEXT: ldr s5, [sp, #248]
+; CHECK-GI-NEXT: mov v19.s[3], v25.s[0]
+; CHECK-GI-NEXT: mov v2.s[3], v6.s[0]
+; CHECK-GI-NEXT: mov v4.s[3], v7.s[0]
+; CHECK-GI-NEXT: mov v21.s[3], v20.s[0]
+; CHECK-GI-NEXT: mov v22.s[3], v5.s[0]
+; CHECK-GI-NEXT: and v1.16b, v1.16b, v17.16b
+; CHECK-GI-NEXT: and v5.16b, v16.16b, v17.16b
+; CHECK-GI-NEXT: and v3.16b, v3.16b, v17.16b
+; CHECK-GI-NEXT: and v6.16b, v18.16b, v17.16b
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v17.16b
+; CHECK-GI-NEXT: and v7.16b, v19.16b, v17.16b
+; CHECK-GI-NEXT: and v2.16b, v2.16b, v17.16b
+; CHECK-GI-NEXT: and v4.16b, v4.16b, v17.16b
+; CHECK-GI-NEXT: and v16.16b, v21.16b, v17.16b
+; CHECK-GI-NEXT: add v1.4s, v1.4s, v5.4s
+; CHECK-GI-NEXT: and v5.16b, v22.16b, v17.16b
+; CHECK-GI-NEXT: add v3.4s, v3.4s, v6.4s
+; CHECK-GI-NEXT: add v0.4s, v0.4s, v7.4s
+; CHECK-GI-NEXT: add v2.4s, v2.4s, v16.4s
+; CHECK-GI-NEXT: stp q1, q3, [x8]
+; CHECK-GI-NEXT: add v1.4s, v4.4s, v5.4s
+; CHECK-GI-NEXT: stp q0, q2, [x8, #32]
+; CHECK-GI-NEXT: str q1, [x8, #64]
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <20 x i8> %s0 to <20 x i32>
%s1s = zext <20 x i8> %s1 to <20 x i32>
@@ -534,98 +1432,165 @@ entry:
}
define <16 x i32> @i12(<16 x i12> %s0, <16 x i12> %s1) {
-; CHECK-LABEL: i12:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: str x23, [sp, #-48]! // 8-byte Folded Spill
-; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w21, -24
-; CHECK-NEXT: .cfi_offset w22, -32
-; CHECK-NEXT: .cfi_offset w23, -48
-; CHECK-NEXT: ldr w13, [sp, #112]
-; CHECK-NEXT: ldr w14, [sp, #144]
-; CHECK-NEXT: fmov s2, w4
-; CHECK-NEXT: ldr w17, [sp, #176]
-; CHECK-NEXT: ldr w19, [sp, #208]
-; CHECK-NEXT: fmov s3, w0
-; CHECK-NEXT: ldr w20, [sp, #80]
-; CHECK-NEXT: ldr w21, [sp, #48]
-; CHECK-NEXT: fmov s5, w13
-; CHECK-NEXT: fmov s4, w19
-; CHECK-NEXT: fmov s6, w17
-; CHECK-NEXT: fmov s7, w14
-; CHECK-NEXT: fmov s0, w20
-; CHECK-NEXT: fmov s1, w21
-; CHECK-NEXT: ldr w10, [sp, #120]
-; CHECK-NEXT: ldr w11, [sp, #152]
-; CHECK-NEXT: ldr w12, [sp, #184]
-; CHECK-NEXT: ldr w15, [sp, #216]
-; CHECK-NEXT: ldr w22, [sp, #88]
-; CHECK-NEXT: ldr w23, [sp, #56]
-; CHECK-NEXT: mov v2.h[1], w5
-; CHECK-NEXT: mov v3.h[1], w1
-; CHECK-NEXT: mov v5.h[1], w10
-; CHECK-NEXT: mov v4.h[1], w15
-; CHECK-NEXT: mov v0.h[1], w22
-; CHECK-NEXT: mov v1.h[1], w23
-; CHECK-NEXT: mov v6.h[1], w12
-; CHECK-NEXT: mov v7.h[1], w11
-; CHECK-NEXT: ldr w8, [sp, #128]
-; CHECK-NEXT: ldr w9, [sp, #160]
-; CHECK-NEXT: ldr w16, [sp, #64]
-; CHECK-NEXT: ldr w18, [sp, #96]
-; CHECK-NEXT: ldr w10, [sp, #192]
-; CHECK-NEXT: ldr w11, [sp, #224]
-; CHECK-NEXT: mov v2.h[2], w6
-; CHECK-NEXT: mov v3.h[2], w2
-; CHECK-NEXT: mov v0.h[2], w18
-; CHECK-NEXT: mov v1.h[2], w16
-; CHECK-NEXT: mov v5.h[2], w8
-; CHECK-NEXT: mov v4.h[2], w11
-; CHECK-NEXT: mov v6.h[2], w10
-; CHECK-NEXT: mov v7.h[2], w9
-; CHECK-NEXT: ldr w12, [sp, #72]
-; CHECK-NEXT: ldr w13, [sp, #104]
-; CHECK-NEXT: ldr w8, [sp, #136]
-; CHECK-NEXT: ldr w9, [sp, #168]
-; CHECK-NEXT: ldr w10, [sp, #200]
-; CHECK-NEXT: ldr w11, [sp, #232]
-; CHECK-NEXT: mov v0.h[3], w13
-; CHECK-NEXT: mov v1.h[3], w12
-; CHECK-NEXT: mov v2.h[3], w7
-; CHECK-NEXT: mov v3.h[3], w3
-; CHECK-NEXT: mov v5.h[3], w8
-; CHECK-NEXT: mov v4.h[3], w11
-; CHECK-NEXT: mov v6.h[3], w10
-; CHECK-NEXT: mov v7.h[3], w9
-; CHECK-NEXT: movi v16.4s, #15, msl #8
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-NEXT: ushll v2.4s, v2.4h, #0
-; CHECK-NEXT: ushll v3.4s, v3.4h, #0
-; CHECK-NEXT: ushll v5.4s, v5.4h, #0
-; CHECK-NEXT: ushll v4.4s, v4.4h, #0
-; CHECK-NEXT: ushll v6.4s, v6.4h, #0
-; CHECK-NEXT: ushll v7.4s, v7.4h, #0
-; CHECK-NEXT: and v17.16b, v0.16b, v16.16b
-; CHECK-NEXT: and v18.16b, v1.16b, v16.16b
-; CHECK-NEXT: and v1.16b, v2.16b, v16.16b
-; CHECK-NEXT: and v0.16b, v3.16b, v16.16b
-; CHECK-NEXT: and v2.16b, v5.16b, v16.16b
-; CHECK-NEXT: and v3.16b, v4.16b, v16.16b
-; CHECK-NEXT: and v4.16b, v6.16b, v16.16b
-; CHECK-NEXT: and v5.16b, v7.16b, v16.16b
-; CHECK-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
-; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: add v3.4s, v17.4s, v3.4s
-; CHECK-NEXT: add v1.4s, v1.4s, v5.4s
-; CHECK-NEXT: add v2.4s, v18.4s, v4.4s
-; CHECK-NEXT: ldr x23, [sp], #48 // 8-byte Folded Reload
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: i12:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: str x23, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w21, -24
+; CHECK-SD-NEXT: .cfi_offset w22, -32
+; CHECK-SD-NEXT: .cfi_offset w23, -48
+; CHECK-SD-NEXT: ldr w13, [sp, #112]
+; CHECK-SD-NEXT: ldr w14, [sp, #144]
+; CHECK-SD-NEXT: fmov s2, w4
+; CHECK-SD-NEXT: ldr w17, [sp, #176]
+; CHECK-SD-NEXT: ldr w19, [sp, #208]
+; CHECK-SD-NEXT: fmov s3, w0
+; CHECK-SD-NEXT: ldr w20, [sp, #80]
+; CHECK-SD-NEXT: ldr w21, [sp, #48]
+; CHECK-SD-NEXT: fmov s5, w13
+; CHECK-SD-NEXT: fmov s4, w19
+; CHECK-SD-NEXT: fmov s6, w17
+; CHECK-SD-NEXT: fmov s7, w14
+; CHECK-SD-NEXT: fmov s0, w20
+; CHECK-SD-NEXT: fmov s1, w21
+; CHECK-SD-NEXT: ldr w10, [sp, #120]
+; CHECK-SD-NEXT: ldr w11, [sp, #152]
+; CHECK-SD-NEXT: ldr w12, [sp, #184]
+; CHECK-SD-NEXT: ldr w15, [sp, #216]
+; CHECK-SD-NEXT: ldr w22, [sp, #88]
+; CHECK-SD-NEXT: ldr w23, [sp, #56]
+; CHECK-SD-NEXT: mov v2.h[1], w5
+; CHECK-SD-NEXT: mov v3.h[1], w1
+; CHECK-SD-NEXT: mov v5.h[1], w10
+; CHECK-SD-NEXT: mov v4.h[1], w15
+; CHECK-SD-NEXT: mov v0.h[1], w22
+; CHECK-SD-NEXT: mov v1.h[1], w23
+; CHECK-SD-NEXT: mov v6.h[1], w12
+; CHECK-SD-NEXT: mov v7.h[1], w11
+; CHECK-SD-NEXT: ldr w8, [sp, #128]
+; CHECK-SD-NEXT: ldr w9, [sp, #160]
+; CHECK-SD-NEXT: ldr w16, [sp, #64]
+; CHECK-SD-NEXT: ldr w18, [sp, #96]
+; CHECK-SD-NEXT: ldr w10, [sp, #192]
+; CHECK-SD-NEXT: ldr w11, [sp, #224]
+; CHECK-SD-NEXT: mov v2.h[2], w6
+; CHECK-SD-NEXT: mov v3.h[2], w2
+; CHECK-SD-NEXT: mov v0.h[2], w18
+; CHECK-SD-NEXT: mov v1.h[2], w16
+; CHECK-SD-NEXT: mov v5.h[2], w8
+; CHECK-SD-NEXT: mov v4.h[2], w11
+; CHECK-SD-NEXT: mov v6.h[2], w10
+; CHECK-SD-NEXT: mov v7.h[2], w9
+; CHECK-SD-NEXT: ldr w12, [sp, #72]
+; CHECK-SD-NEXT: ldr w13, [sp, #104]
+; CHECK-SD-NEXT: ldr w8, [sp, #136]
+; CHECK-SD-NEXT: ldr w9, [sp, #168]
+; CHECK-SD-NEXT: ldr w10, [sp, #200]
+; CHECK-SD-NEXT: ldr w11, [sp, #232]
+; CHECK-SD-NEXT: mov v0.h[3], w13
+; CHECK-SD-NEXT: mov v1.h[3], w12
+; CHECK-SD-NEXT: mov v2.h[3], w7
+; CHECK-SD-NEXT: mov v3.h[3], w3
+; CHECK-SD-NEXT: mov v5.h[3], w8
+; CHECK-SD-NEXT: mov v4.h[3], w11
+; CHECK-SD-NEXT: mov v6.h[3], w10
+; CHECK-SD-NEXT: mov v7.h[3], w9
+; CHECK-SD-NEXT: movi v16.4s, #15, msl #8
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-SD-NEXT: ushll v2.4s, v2.4h, #0
+; CHECK-SD-NEXT: ushll v3.4s, v3.4h, #0
+; CHECK-SD-NEXT: ushll v5.4s, v5.4h, #0
+; CHECK-SD-NEXT: ushll v4.4s, v4.4h, #0
+; CHECK-SD-NEXT: ushll v6.4s, v6.4h, #0
+; CHECK-SD-NEXT: ushll v7.4s, v7.4h, #0
+; CHECK-SD-NEXT: and v17.16b, v0.16b, v16.16b
+; CHECK-SD-NEXT: and v18.16b, v1.16b, v16.16b
+; CHECK-SD-NEXT: and v1.16b, v2.16b, v16.16b
+; CHECK-SD-NEXT: and v0.16b, v3.16b, v16.16b
+; CHECK-SD-NEXT: and v2.16b, v5.16b, v16.16b
+; CHECK-SD-NEXT: and v3.16b, v4.16b, v16.16b
+; CHECK-SD-NEXT: and v4.16b, v6.16b, v16.16b
+; CHECK-SD-NEXT: and v5.16b, v7.16b, v16.16b
+; CHECK-SD-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-SD-NEXT: add v0.4s, v0.4s, v2.4s
+; CHECK-SD-NEXT: add v3.4s, v17.4s, v3.4s
+; CHECK-SD-NEXT: add v1.4s, v1.4s, v5.4s
+; CHECK-SD-NEXT: add v2.4s, v18.4s, v4.4s
+; CHECK-SD-NEXT: ldr x23, [sp], #48 // 8-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: i12:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov s1, w0
+; CHECK-GI-NEXT: fmov s4, w4
+; CHECK-GI-NEXT: ldr s0, [sp]
+; CHECK-GI-NEXT: ldr s20, [sp, #8]
+; CHECK-GI-NEXT: ldr s2, [sp, #32]
+; CHECK-GI-NEXT: ldr s21, [sp, #40]
+; CHECK-GI-NEXT: ldr s16, [sp, #64]
+; CHECK-GI-NEXT: ldr s22, [sp, #72]
+; CHECK-GI-NEXT: ldr s17, [sp, #96]
+; CHECK-GI-NEXT: ldr s23, [sp, #104]
+; CHECK-GI-NEXT: mov v1.s[1], w1
+; CHECK-GI-NEXT: mov v4.s[1], w5
+; CHECK-GI-NEXT: ldr s18, [sp, #128]
+; CHECK-GI-NEXT: ldr s24, [sp, #136]
+; CHECK-GI-NEXT: mov v0.s[1], v20.s[0]
+; CHECK-GI-NEXT: ldr s19, [sp, #160]
+; CHECK-GI-NEXT: ldr s25, [sp, #168]
+; CHECK-GI-NEXT: mov v2.s[1], v21.s[0]
+; CHECK-GI-NEXT: mov v16.s[1], v22.s[0]
+; CHECK-GI-NEXT: mov v17.s[1], v23.s[0]
+; CHECK-GI-NEXT: mov v18.s[1], v24.s[0]
+; CHECK-GI-NEXT: mov v19.s[1], v25.s[0]
+; CHECK-GI-NEXT: ldr s6, [sp, #16]
+; CHECK-GI-NEXT: ldr s7, [sp, #48]
+; CHECK-GI-NEXT: ldr s20, [sp, #80]
+; CHECK-GI-NEXT: ldr s21, [sp, #112]
+; CHECK-GI-NEXT: ldr s22, [sp, #144]
+; CHECK-GI-NEXT: ldr s23, [sp, #176]
+; CHECK-GI-NEXT: mov v1.s[2], w2
+; CHECK-GI-NEXT: mov v4.s[2], w6
+; CHECK-GI-NEXT: mov v0.s[2], v6.s[0]
+; CHECK-GI-NEXT: mov v2.s[2], v7.s[0]
+; CHECK-GI-NEXT: mov v16.s[2], v20.s[0]
+; CHECK-GI-NEXT: mov v17.s[2], v21.s[0]
+; CHECK-GI-NEXT: mov v18.s[2], v22.s[0]
+; CHECK-GI-NEXT: mov v19.s[2], v23.s[0]
+; CHECK-GI-NEXT: ldr s3, [sp, #24]
+; CHECK-GI-NEXT: ldr s5, [sp, #56]
+; CHECK-GI-NEXT: ldr s6, [sp, #88]
+; CHECK-GI-NEXT: ldr s7, [sp, #120]
+; CHECK-GI-NEXT: ldr s20, [sp, #152]
+; CHECK-GI-NEXT: ldr s21, [sp, #184]
+; CHECK-GI-NEXT: mov v1.s[3], w3
+; CHECK-GI-NEXT: mov v4.s[3], w7
+; CHECK-GI-NEXT: movi v22.4s, #15, msl #8
+; CHECK-GI-NEXT: mov v0.s[3], v3.s[0]
+; CHECK-GI-NEXT: mov v2.s[3], v5.s[0]
+; CHECK-GI-NEXT: mov v16.s[3], v6.s[0]
+; CHECK-GI-NEXT: mov v17.s[3], v7.s[0]
+; CHECK-GI-NEXT: mov v18.s[3], v20.s[0]
+; CHECK-GI-NEXT: mov v19.s[3], v21.s[0]
+; CHECK-GI-NEXT: and v1.16b, v1.16b, v22.16b
+; CHECK-GI-NEXT: and v3.16b, v4.16b, v22.16b
+; CHECK-GI-NEXT: and v4.16b, v0.16b, v22.16b
+; CHECK-GI-NEXT: and v5.16b, v2.16b, v22.16b
+; CHECK-GI-NEXT: and v0.16b, v16.16b, v22.16b
+; CHECK-GI-NEXT: and v2.16b, v17.16b, v22.16b
+; CHECK-GI-NEXT: and v6.16b, v18.16b, v22.16b
+; CHECK-GI-NEXT: and v7.16b, v19.16b, v22.16b
+; CHECK-GI-NEXT: add v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: add v1.4s, v3.4s, v2.4s
+; CHECK-GI-NEXT: add v2.4s, v4.4s, v6.4s
+; CHECK-GI-NEXT: add v3.4s, v5.4s, v7.4s
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <16 x i12> %s0 to <16 x i32>
%s1s = zext <16 x i12> %s1 to <16 x i32>
@@ -634,15 +1599,27 @@ entry:
}
define <16 x i32> @sub_zz(<16 x i8> %s0, <16 x i8> %s1) {
-; CHECK-LABEL: sub_zz:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: usubl v2.8h, v0.8b, v1.8b
-; CHECK-NEXT: usubl2 v4.8h, v0.16b, v1.16b
-; CHECK-NEXT: sshll v0.4s, v2.4h, #0
-; CHECK-NEXT: sshll2 v3.4s, v4.8h, #0
-; CHECK-NEXT: sshll2 v1.4s, v2.8h, #0
-; CHECK-NEXT: sshll v2.4s, v4.4h, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sub_zz:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: usubl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: usubl2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: sshll v0.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v3.4s, v4.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v2.4s, v4.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sub_zz:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: ushll2 v4.8h, v0.16b, #0
+; CHECK-GI-NEXT: ushll2 v5.8h, v1.16b, #0
+; CHECK-GI-NEXT: usubl v0.4s, v2.4h, v3.4h
+; CHECK-GI-NEXT: usubl2 v1.4s, v2.8h, v3.8h
+; CHECK-GI-NEXT: usubl v2.4s, v4.4h, v5.4h
+; CHECK-GI-NEXT: usubl2 v3.4s, v4.8h, v5.8h
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <16 x i8> %s0 to <16 x i32>
%s1s = zext <16 x i8> %s1 to <16 x i32>
@@ -651,15 +1628,27 @@ entry:
}
define <16 x i32> @sub_ss(<16 x i8> %s0, <16 x i8> %s1) {
-; CHECK-LABEL: sub_ss:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ssubl v2.8h, v0.8b, v1.8b
-; CHECK-NEXT: ssubl2 v4.8h, v0.16b, v1.16b
-; CHECK-NEXT: sshll v0.4s, v2.4h, #0
-; CHECK-NEXT: sshll2 v3.4s, v4.8h, #0
-; CHECK-NEXT: sshll2 v1.4s, v2.8h, #0
-; CHECK-NEXT: sshll v2.4s, v4.4h, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sub_ss:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ssubl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: ssubl2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: sshll v0.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v3.4s, v4.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v2.4s, v4.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sub_ss:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll2 v4.8h, v0.16b, #0
+; CHECK-GI-NEXT: sshll2 v5.8h, v1.16b, #0
+; CHECK-GI-NEXT: ssubl v0.4s, v2.4h, v3.4h
+; CHECK-GI-NEXT: ssubl2 v1.4s, v2.8h, v3.8h
+; CHECK-GI-NEXT: ssubl v2.4s, v4.4h, v5.4h
+; CHECK-GI-NEXT: ssubl2 v3.4s, v4.8h, v5.8h
+; CHECK-GI-NEXT: ret
entry:
%s0s = sext <16 x i8> %s0 to <16 x i32>
%s1s = sext <16 x i8> %s1 to <16 x i32>
@@ -668,17 +1657,33 @@ entry:
}
define <16 x i32> @sub_zs(<16 x i8> %s0, <16 x i8> %s1) {
-; CHECK-LABEL: sub_zs:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ushll v2.8h, v0.8b, #0
-; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0
-; CHECK-NEXT: ssubw v2.8h, v2.8h, v1.8b
-; CHECK-NEXT: ssubw2 v4.8h, v0.8h, v1.16b
-; CHECK-NEXT: sshll v0.4s, v2.4h, #0
-; CHECK-NEXT: sshll2 v3.4s, v4.8h, #0
-; CHECK-NEXT: sshll2 v1.4s, v2.8h, #0
-; CHECK-NEXT: sshll v2.4s, v4.4h, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sub_zs:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-SD-NEXT: ssubw v2.8h, v2.8h, v1.8b
+; CHECK-SD-NEXT: ssubw2 v4.8h, v0.8h, v1.16b
+; CHECK-SD-NEXT: sshll v0.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v3.4s, v4.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v2.4s, v4.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sub_zs:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: sshll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll2 v4.8h, v1.16b, #0
+; CHECK-GI-NEXT: ushll v1.4s, v2.4h, #0
+; CHECK-GI-NEXT: ushll2 v2.4s, v2.8h, #0
+; CHECK-GI-NEXT: ushll v5.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v6.4s, v0.8h, #0
+; CHECK-GI-NEXT: ssubw v0.4s, v1.4s, v3.4h
+; CHECK-GI-NEXT: ssubw2 v1.4s, v2.4s, v3.8h
+; CHECK-GI-NEXT: ssubw v2.4s, v5.4s, v4.4h
+; CHECK-GI-NEXT: ssubw2 v3.4s, v6.4s, v4.8h
+; CHECK-GI-NEXT: ret
entry:
%s0s = zext <16 x i8> %s0 to <16 x i32>
%s1s = sext <16 x i8> %s1 to <16 x i32>
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