[llvm] [InstCombine] Simplify further when shift is half bitwidth (PR #93677)

[Nikita Popov via llvm-commits]

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@@ -1463,11 +1463,17 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
     if (match(Op0, m_NUWMul(m_Value(X), m_APInt(MulC)))) {
       if (BitWidth > 2 && (*MulC - 1).isPowerOf2() &&
           MulC->logBase2() == ShAmtC) {
+
         // Look for a "splat" mul pattern - it replicates bits across each half
         // of a value, so a right shift is just a mask of the low bits:
-        // lshr i[2N] (mul nuw X, (2^N)+1), N --> and iN X, (2^N)-1
+        // lshr i[2N] (mul nuw X, (2^N)+1), N --> X
         if (ShAmtC * 2 == BitWidth)
-          return BinaryOperator::CreateAnd(X, ConstantInt::get(Ty, *MulC - 2));
+          return replaceInstUsesWith(I, X);
+
+        KnownBits KnownX =
+            computeKnownBits(X, /* Depth */ 0, cast<Instruction>(Op0));
+        if (KnownX.countMaxActiveBits() <= ShAmtC)
+          return replaceInstUsesWith(I, X);
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nikic wrote:

I don't understand the purpose of this special case. If the top bits are all zero, then the generated `lshr(X,N)` will fold to zero and the result will be just `X`.

I think the only additional fold this would enable is the extra-use case, which is not a case we're interested int.

https://github.com/llvm/llvm-project/pull/93677