[llvm] [llvm][test] Fix filecheck annotation typos (PR #93673)
via llvm-commits
llvm-commits at lists.llvm.org
Wed May 29 05:22:17 PDT 2024
https://github.com/klensy created https://github.com/llvm/llvm-project/pull/93673
Moved fixes for llvm from #91854, plus few additional.
>From fb1dd1bcba5d3ed086f248b5bcca61295137bee9 Mon Sep 17 00:00:00 2001
From: klensy <nightouser at gmail.com>
Date: Wed, 29 May 2024 15:14:10 +0300
Subject: [PATCH 1/5] fixes moved from #91854
---
.../AArch64/sve-shuffle-broadcast.ll | 2 +-
.../irreducible/diverged-entry-headers.ll | 2 +-
llvm/test/Assembler/bfloat.ll | 8 +++----
llvm/test/CodeGen/AArch64/arm64_32-atomics.ll | 20 ++++++++---------
.../CodeGen/AArch64/arm64ec-entry-thunks.ll | 2 +-
llvm/test/CodeGen/AArch64/fpimm.ll | 2 +-
...tliner-retaddr-sign-diff-scope-same-key.ll | 2 +-
.../AArch64/speculation-hardening-sls.ll | 4 ++--
.../stp-opt-with-renaming-undef-assert.mir | 2 +-
llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 4 ++--
.../test/CodeGen/AMDGPU/dpp_combine_gfx11.mir | 10 ++++-----
llvm/test/CodeGen/ARM/dsp-loop-indexing.ll | 2 +-
llvm/test/CodeGen/ARM/shifter_operand.ll | 1 -
.../CodeGen/ARM/speculation-hardening-sls.ll | 2 +-
llvm/test/CodeGen/ARM/sxt_rot.ll | 1 -
.../test/CodeGen/Mips/optimizeAndPlusShift.ll | 18 +++++++--------
llvm/test/CodeGen/NVPTX/idioms.ll | 10 ++++-----
llvm/test/CodeGen/SPARC/inlineasm.ll | 2 +-
.../intel-usm-addrspaces.ll | 2 +-
llvm/test/CodeGen/SystemZ/prefetch-04.ll | 2 +-
.../Thumb2/LowOverheadLoops/branch-targets.ll | 6 ++---
llvm/test/CodeGen/X86/global-sections.ll | 4 ++--
llvm/test/CodeGen/X86/tailregccpic.ll | 4 ++--
.../InstrRef/livedebugvalues_illegal_locs.mir | 6 ++---
.../InstrRef/single-assign-propagation.mir | 6 ++---
llvm/test/MC/ARM/coff-relocations.s | 2 +-
.../Mips/mips32r6/valid-mips32r6.txt | 6 ++---
.../Mips/mips64r6/valid-mips64r6.txt | 6 ++---
llvm/test/MC/Mips/expansion-jal-sym-pic.s | 12 +++++-----
llvm/test/MC/Mips/macro-rem.s | 2 +-
llvm/test/MC/RISCV/zicfiss-valid.s | 12 +++++-----
.../Coroutines/coro-debug-coro-frame.ll | 2 +-
.../Transforms/Inline/update_invoke_prof.ll | 2 +-
.../InstCombine/lifetime-sanitizer.ll | 2 +-
llvm/test/Transforms/LoopUnroll/peel-loop2.ll | 2 +-
.../AArch64/nontemporal-load-store.ll | 22 +++++++++----------
llvm/test/Transforms/LoopVectorize/memdep.ll | 2 +-
...wrapping-pointer-non-integral-addrspace.ll | 2 +-
.../X86/good-prototype.ll | 2 +-
.../pseudo-probe-selectionDAG.ll | 4 ++--
llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll | 2 +-
llvm/test/tools/llvm-ar/replace-update.test | 2 +-
.../Inputs/binary-formats.canonical.json | 2 +-
.../tools/llvm-objdump/ELF/ARM/v5te-subarch.s | 2 +-
44 files changed, 105 insertions(+), 107 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll b/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll
index a2526d9f5591a..c2aab35194831 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll
@@ -31,7 +31,7 @@ define void @broadcast() #0{
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %24 = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
-; CHECK-NETX: Cost Model: Found an estimated cost of 0 for instruction: ret void
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
%zero = shufflevector <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%1 = shufflevector <vscale x 32 x i8> undef, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll
index 335026dc9b62b..efad77b684a75 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll
@@ -90,7 +90,7 @@ S:
br i1 %cond.uni, label %exit, label %T
T:
-; CHECK-NIT: DIVERGENT: %tt.phi = phi i32
+; CHECK-NOT: DIVERGENT: %tt.phi = phi i32
%tt.phi = phi i32 [ %ss, %S ], [ %a, %entry ]
%tt = add i32 %b, 1
br label %P
diff --git a/llvm/test/Assembler/bfloat.ll b/llvm/test/Assembler/bfloat.ll
index 3a3b4c2b277db..6f935c5dac154 100644
--- a/llvm/test/Assembler/bfloat.ll
+++ b/llvm/test/Assembler/bfloat.ll
@@ -37,25 +37,25 @@ define float @check_bfloat_convert() {
ret float %tmp
}
-; ASSEM-DISASS-LABEL @snan_bfloat
+; ASSEM-DISASS-LABEL: @snan_bfloat
define bfloat @snan_bfloat() {
; ASSEM-DISASS: ret bfloat 0xR7F81
ret bfloat 0xR7F81
}
-; ASSEM-DISASS-LABEL @qnan_bfloat
+; ASSEM-DISASS-LABEL: @qnan_bfloat
define bfloat @qnan_bfloat() {
; ASSEM-DISASS: ret bfloat 0xR7FC0
ret bfloat 0xR7FC0
}
-; ASSEM-DISASS-LABEL @pos_inf_bfloat
+; ASSEM-DISASS-LABEL: @pos_inf_bfloat
define bfloat @pos_inf_bfloat() {
; ASSEM-DISASS: ret bfloat 0xR7F80
ret bfloat 0xR7F80
}
-; ASSEM-DISASS-LABEL @neg_inf_bfloat
+; ASSEM-DISASS-LABEL: @neg_inf_bfloat
define bfloat @neg_inf_bfloat() {
; ASSEM-DISASS: ret bfloat 0xRFF80
ret bfloat 0xRFF80
diff --git a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
index 0000262e833da..19b9205dc1786 100644
--- a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
+++ b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
@@ -2,70 +2,70 @@
; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS
define i8 @test_load_8(ptr %addr) {
-; CHECK-LABAL: test_load_8:
+; CHECK-LABEL: test_load_8:
; CHECK: ldarb w0, [x0]
%val = load atomic i8, ptr %addr seq_cst, align 1
ret i8 %val
}
define i16 @test_load_16(ptr %addr) {
-; CHECK-LABAL: test_load_16:
+; CHECK-LABEL: test_load_16:
; CHECK: ldarh w0, [x0]
%val = load atomic i16, ptr %addr acquire, align 2
ret i16 %val
}
define i32 @test_load_32(ptr %addr) {
-; CHECK-LABAL: test_load_32:
+; CHECK-LABEL: test_load_32:
; CHECK: ldar w0, [x0]
%val = load atomic i32, ptr %addr seq_cst, align 4
ret i32 %val
}
define i64 @test_load_64(ptr %addr) {
-; CHECK-LABAL: test_load_64:
+; CHECK-LABEL: test_load_64:
; CHECK: ldar x0, [x0]
%val = load atomic i64, ptr %addr seq_cst, align 8
ret i64 %val
}
define ptr @test_load_ptr(ptr %addr) {
-; CHECK-LABAL: test_load_ptr:
+; CHECK-LABEL: test_load_ptr:
; CHECK: ldar w0, [x0]
%val = load atomic ptr, ptr %addr seq_cst, align 8
ret ptr %val
}
define void @test_store_8(ptr %addr) {
-; CHECK-LABAL: test_store_8:
+; CHECK-LABEL: test_store_8:
; CHECK: stlrb wzr, [x0]
store atomic i8 0, ptr %addr seq_cst, align 1
ret void
}
define void @test_store_16(ptr %addr) {
-; CHECK-LABAL: test_store_16:
+; CHECK-LABEL: test_store_16:
; CHECK: stlrh wzr, [x0]
store atomic i16 0, ptr %addr seq_cst, align 2
ret void
}
define void @test_store_32(ptr %addr) {
-; CHECK-LABAL: test_store_32:
+; CHECK-LABEL: test_store_32:
; CHECK: stlr wzr, [x0]
store atomic i32 0, ptr %addr seq_cst, align 4
ret void
}
define void @test_store_64(ptr %addr) {
-; CHECK-LABAL: test_store_64:
+; CHECK-LABEL: test_store_64:
; CHECK: stlr xzr, [x0]
store atomic i64 0, ptr %addr seq_cst, align 8
ret void
}
define void @test_store_ptr(ptr %addr) {
-; CHECK-LABAL: test_store_ptr:
+; CHECK-LABEL: test_store_ptr:
; CHECK: stlr wzr, [x0]
store atomic ptr null, ptr %addr seq_cst, align 8
ret void
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
index e9556b9d5cbee..e93fcec822846 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm64ec-pc-windows-msvc < %s | FileCheck %s
define void @no_op() nounwind {
-; CHECK-LABEL .def $ientry_thunk$cdecl$v$v;
+; CHECK-LABEL: .def $ientry_thunk$cdecl$v$v;
; CHECK: .section .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$v$v
; CHECK: // %bb.0:
; CHECK-NEXT: stp q6, q7, [sp, #-176]! // 32-byte Folded Spill
diff --git a/llvm/test/CodeGen/AArch64/fpimm.ll b/llvm/test/CodeGen/AArch64/fpimm.ll
index b92bb4245c7f3..e2944243338f5 100644
--- a/llvm/test/CodeGen/AArch64/fpimm.ll
+++ b/llvm/test/CodeGen/AArch64/fpimm.ll
@@ -38,7 +38,7 @@ define void @check_double() {
; 64-bit ORR followed by MOVK.
; CHECK-DAG: mov [[XFP0:x[0-9]+]], #1082331758844
; CHECK-DAG: movk [[XFP0]], #64764, lsl #16
-; CHECk-DAG: fmov {{d[0-9]+}}, [[XFP0]]
+; CHECK-DAG: fmov {{d[0-9]+}}, [[XFP0]]
%newval3 = fadd double %val, 0xFCFCFC00FC
store volatile double %newval3, ptr @varf64
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
index a5757a70843a9..fa63df35ac857 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
@@ -28,7 +28,7 @@ define void @a() "sign-return-address"="all" {
}
define void @b() "sign-return-address"="non-leaf" {
-; CHECK-LABE: b: // @b
+; CHECK-LABEL: b: // @b
; V8A-NOT: hint #25
; V83A-NOT: paciasp
; CHECK-NOT: .cfi_negate_ra_state
diff --git a/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll b/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
index f380b2d05d863..fe08fa5642574 100644
--- a/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
+++ b/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
@@ -192,7 +192,7 @@ entry:
; CHECK: .Lfunc_end
}
-; HARDEN-label: __llvm_slsblr_thunk_x0:
+; HARDEN-LABEL: __llvm_slsblr_thunk_x0:
; HARDEN: mov x16, x0
; HARDEN: br x16
; ISBDSB-NEXT: dsb sy
@@ -208,7 +208,7 @@ entry:
; HARDEN-COMDAT-OFF-NOT: .hidden __llvm_slsblr_thunk_x19
; HARDEN-COMDAT-OFF-NOT: .weak __llvm_slsblr_thunk_x19
; HARDEN-COMDAT-OFF: .type __llvm_slsblr_thunk_x19, at function
-; HARDEN-label: __llvm_slsblr_thunk_x19:
+; HARDEN-LABEL: __llvm_slsblr_thunk_x19:
; HARDEN: mov x16, x19
; HARDEN: br x16
; ISBDSB-NEXT: dsb sy
diff --git a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
index 66d2067b531a3..bfdb1763776b4 100644
--- a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
+++ b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
@@ -12,7 +12,7 @@
# This test also checks that pairwise store STP is generated.
-# CHECK-LABLE: test
+# CHECK-LABEL: test
# CHECK: bb.0:
# CHECK-NEXT: liveins: $x0, $x17, $x18
# CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64)
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
index 50423c59eabe9..526d5c946ec7f 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
@@ -108,7 +108,7 @@ define amdgpu_kernel void @use_global_to_flat_addrspacecast(ptr addrspace(1) %pt
}
; no-op
-; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
+; HSA-LABEL: {{^}}use_constant_to_flat_addrspacecast:
; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
@@ -119,7 +119,7 @@ define amdgpu_kernel void @use_constant_to_flat_addrspacecast(ptr addrspace(4) %
ret void
}
-; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast:
+; HSA-LABEL: {{^}}use_constant_to_global_addrspacecast:
; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
index 29621a0477418..1151bde02ef62 100644
--- a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
+++ b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
@@ -4,7 +4,7 @@
---
-# GCN-label: name: vop3
+# GCN-LABEL: name: vop3
# GCN: %6:vgpr_32, %7:sreg_32_xm0_xexec = V_SUBBREV_U32_e64_dpp %3, %0, %1, %5, 1, 1, 15, 15, 1, implicit $exec
# GCN: %8:vgpr_32 = V_CVT_PK_U8_F32_e64_dpp %3, 4, %0, 2, %2, 2, %1, 1, 1, 15, 15, 1, implicit $mode, implicit $exec
# GCN: %10:vgpr_32 = V_MED3_F32_e64 0, %9, 0, %0, 0, 12345678, 0, 0, implicit $mode, implicit $exec
@@ -37,7 +37,7 @@ body: |
...
---
-# GCN-label: name: vop3_sgpr_src1
+# GCN-LABEL: name: vop3_sgpr_src1
# GCN: %6:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, %1, 0, %2, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
# GFX1100: %8:vgpr_32 = V_MED3_F32_e64 0, %7, 0, %2, 0, %1, 0, 0, implicit $mode, implicit $exec
# GFX1150: %8:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, %2, 0, %1, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
@@ -81,7 +81,7 @@ body: |
---
# Regression test for src_modifiers on base u16 opcode
-# GCN-label: name: vop3_u16
+# GCN-LABEL: name: vop3_u16
# GCN: %5:vgpr_32 = V_ADD_NC_U16_e64_dpp %3, 0, %1, 0, %3, 0, 0, 1, 15, 15, 1, implicit $exec
# GCN: %7:vgpr_32 = V_ADD_NC_U16_e64_dpp %3, 1, %5, 2, %5, 0, 0, 1, 15, 15, 1, implicit $exec
# GCN: %9:vgpr_32 = V_ADD_NC_U16_e64 4, %8, 8, %7, 0, 0, implicit $exec
@@ -205,7 +205,7 @@ body: |
...
# do not combine, dpp arg used twice
-# GCN-label: name: dpp_arg_twice
+# GCN-LABEL: name: dpp_arg_twice
# GCN: %4:vgpr_32 = V_FMA_F32_e64 1, %1, 2, %3, 2, %3, 1, 2, implicit $mode, implicit $exec
# GCN: %6:vgpr_32 = V_FMA_F32_e64 2, %5, 2, %1, 2, %5, 1, 2, implicit $mode, implicit $exec
# GCN: %8:vgpr_32 = V_FMA_F32_e64 2, %7, 2, %7, 2, %1, 1, 2, implicit $mode, implicit $exec
@@ -231,7 +231,7 @@ body: |
...
# when the dpp source isn't a src0 operand the operation should be commuted if possible
-# GCN-label: name: dpp_commute_e64
+# GCN-LABEL: name: dpp_commute_e64
# GCN: %4:vgpr_32 = V_MUL_U32_U24_e64_dpp %1, %0, %1, 1, 1, 14, 15, 0, implicit $exec
# GCN: %7:vgpr_32 = V_FMA_F32_e64_dpp %5, 2, %0, 1, %1, 2, %1, 1, 2, 1, 15, 15, 1, implicit $mode, implicit $exec
# GCN: %10:vgpr_32 = V_SUBREV_U32_e64_dpp %1, %0, %1, 1, 1, 14, 15, 0, implicit $exec
diff --git a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
index 9fb64471e9881..892e66aed4e5f 100644
--- a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
+++ b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
@@ -22,7 +22,7 @@
; CHECK-DEFAULT: ldr{{.*}}, #4]
; CHECK-DEFAULT: str{{.*}}, #4]
; CHECK-DEFAULT: ldr{{.*}}, #8]!
-; CHECK-DEAFULT: ldr{{.*}}, #8]!
+; CHECK-DEFAULT: ldr{{.*}}, #8]!
; CHECK-DEFAULT: str{{.*}}, #8]!
; CHECK-COMPLEX: ldr{{.*}}, #8]!
diff --git a/llvm/test/CodeGen/ARM/shifter_operand.ll b/llvm/test/CodeGen/ARM/shifter_operand.ll
index bf2e8aa911c64..00922b1bf2492 100644
--- a/llvm/test/CodeGen/ARM/shifter_operand.ll
+++ b/llvm/test/CodeGen/ARM/shifter_operand.ll
@@ -121,7 +121,6 @@ define i32 @test_orr_extract_from_mul_1(i32 %x, i32 %y) {
; CHECK-THUMB-NEXT: orrs r0, r1
; CHECK-THUMB-NEXT: bx lr
entry:
-; CHECk-THUMB: orrs r0, r1
%mul = mul i32 %y, 63767
%or = or i32 %mul, %x
ret i32 %or
diff --git a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
index f25d73a12246f..1f60f120dc86a 100644
--- a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
+++ b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
@@ -248,7 +248,7 @@ entry:
; HARDEN-COMDAT-OFF-NOT: .hidden {{__llvm_slsblr_thunk_(arm|thumb)_r5}}
; HARDEN-COMDAT-OFF-NOT: .weak {{__llvm_slsblr_thunk_(arm|thumb)_r5}}
; HARDEN-COMDAT-OFF: .type {{__llvm_slsblr_thunk_(arm|thumb)_r5}},%function
-; HARDEN-label: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}:
+; HARDEN-LABEL: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}:
; HARDEN: bx r5
; ISBDSB-NEXT: dsb sy
; ISBDSB-NEXT: isb
diff --git a/llvm/test/CodeGen/ARM/sxt_rot.ll b/llvm/test/CodeGen/ARM/sxt_rot.ll
index e9649c7a7fd9a..775e45201105c 100644
--- a/llvm/test/CodeGen/ARM/sxt_rot.ll
+++ b/llvm/test/CodeGen/ARM/sxt_rot.ll
@@ -22,7 +22,6 @@ define signext i8 @test1(i32 %A) {
; CHECK-V7: @ %bb.0:
; CHECK-V7-NEXT: sbfx r0, r0, #8, #8
; CHECK-V7-NEXT: bx lr
-; CHECk-V7: sbfx r0, r0, #8, #8
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
diff --git a/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll b/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll
index bf69adf6702f0..58920483e24bf 100644
--- a/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll
+++ b/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll
@@ -3,11 +3,11 @@
; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64
define i32 @shl_32(i32 %a, i32 %b) {
-; MIPS32-LABLE: shl_32:
+; MIPS32-LABEL: shl_32:
; MIPS32: # %bb.0:
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: sllv $2, $4, $5
-; MIPS64-LABLE: shl_32:
+; MIPS64-LABEL: shl_32:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: sll $2, $4, 0
@@ -19,11 +19,11 @@ define i32 @shl_32(i32 %a, i32 %b) {
}
define i32 @lshr_32(i32 %a, i32 %b) {
-; MIPS32-LABLE: lshr_32:
+; MIPS32-LABEL: lshr_32:
; MIPS32: # %bb.0:
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: srlv $2, $4, $5
-; MIPS64-LABLE: lshr_32:
+; MIPS64-LABEL: lshr_32:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: sll $2, $4, 0
@@ -35,11 +35,11 @@ define i32 @lshr_32(i32 %a, i32 %b) {
}
define i32 @ashr_32(i32 %a, i32 %b) {
-; MIPS32-LABLE: ashr_32:
+; MIPS32-LABEL: ashr_32:
; MIPS32: # %bb.0:
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: srav $2, $4, $5
-; MIPS64-LABLE: ashr_32:
+; MIPS64-LABEL: ashr_32:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: sll $2, $4, 0
@@ -51,7 +51,7 @@ define i32 @ashr_32(i32 %a, i32 %b) {
}
define i64 @shl_64(i64 %a, i64 %b) {
-; MIPS64-LABLE: shl_64:
+; MIPS64-LABEL: shl_64:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: jr $ra
@@ -62,7 +62,7 @@ define i64 @shl_64(i64 %a, i64 %b) {
}
define i64 @lshr_64(i64 %a, i64 %b) {
-; MIPS64-LABLE: lshr_64:
+; MIPS64-LABEL: lshr_64:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: jr $ra
@@ -73,7 +73,7 @@ define i64 @lshr_64(i64 %a, i64 %b) {
}
define i64 @ashr_64(i64 %a, i64 %b) {
-; MIPS64-LABLE: ashr_64:
+; MIPS64-LABEL: ashr_64:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/NVPTX/idioms.ll b/llvm/test/CodeGen/NVPTX/idioms.ll
index e8fe47c303f92..0669d2a3717cb 100644
--- a/llvm/test/CodeGen/NVPTX/idioms.ll
+++ b/llvm/test/CodeGen/NVPTX/idioms.ll
@@ -42,7 +42,7 @@ define %struct.S16 @i32_to_2xi16(i32 noundef %in) {
%high = trunc i32 %high32 to i16
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_param_0];
; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]];
-; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
+; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
%s1 = insertvalue %struct.S16 poison, i16 %low, 0
%s = insertvalue %struct.S16 %s1, i16 %high, 1
ret %struct.S16 %s
@@ -56,7 +56,7 @@ define %struct.S16 @i32_to_2xi16_lh(i32 noundef %in) {
%low = trunc i32 %in to i16
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_lh_param_0];
; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]];
-; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
+; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
%s1 = insertvalue %struct.S16 poison, i16 %low, 0
%s = insertvalue %struct.S16 %s1, i16 %high, 1
ret %struct.S16 %s
@@ -84,7 +84,7 @@ define %struct.S32 @i64_to_2xi32(i64 noundef %in) {
%high = trunc i64 %high64 to i32
; CHECK: ld.param.u64 %[[R64:rd[0-9]+]], [i64_to_2xi32_param_0];
; CHECK-DAG: cvt.u32.u64 %r{{[0-9+]}}, %[[R64]];
-; CHECK-DAG mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]];
+; CHECK-DAG: mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]];
%s1 = insertvalue %struct.S32 poison, i32 %low, 0
%s = insertvalue %struct.S32 %s1, i32 %high, 1
ret %struct.S32 %s
@@ -114,8 +114,8 @@ define %struct.S16 @i32_to_2xi16_shr(i32 noundef %i){
%h = trunc i32 %h32 to i16
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_shr_param_0];
; CHECK: shr.s32 %[[R32H:r[0-9]+]], %[[R32]], 16;
-; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
-; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]];
+; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
+; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]];
%s0 = insertvalue %struct.S16 poison, i16 %l, 0
%s1 = insertvalue %struct.S16 %s0, i16 %h, 1
ret %struct.S16 %s1
diff --git a/llvm/test/CodeGen/SPARC/inlineasm.ll b/llvm/test/CodeGen/SPARC/inlineasm.ll
index 9817d7c6971f5..786e9f3eb1e13 100644
--- a/llvm/test/CodeGen/SPARC/inlineasm.ll
+++ b/llvm/test/CodeGen/SPARC/inlineasm.ll
@@ -144,7 +144,7 @@ entry:
ret void
}
-; CHECK-label:test_twinword
+; CHECK-LABEL:test_twinword
; CHECK: rd %asr5, %i1
; CHECK: srlx %i1, 32, %i0
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
index b5df462bd8fa9..f5f1382a35fca 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
@@ -6,7 +6,7 @@
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-: Capability USMStorageClassesINTEL
-; CHECK-SPIRV-WITHOUT-NO: Capability USMStorageClassesINTEL
+; CHECK-SPIRV-WITHOUT-NOT: Capability USMStorageClassesINTEL
; CHECK-SPIRV-EXT-DAG: %[[DevTy:[0-9]+]] = OpTypePointer DeviceOnlyINTEL %[[#]]
; CHECK-SPIRV-EXT-DAG: %[[HostTy:[0-9]+]] = OpTypePointer HostOnlyINTEL %[[#]]
; CHECK-SPIRV-DAG: %[[CrsWrkTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[#]]
diff --git a/llvm/test/CodeGen/SystemZ/prefetch-04.ll b/llvm/test/CodeGen/SystemZ/prefetch-04.ll
index 61a2a1460c583..10755bdb66eb5 100644
--- a/llvm/test/CodeGen/SystemZ/prefetch-04.ll
+++ b/llvm/test/CodeGen/SystemZ/prefetch-04.ll
@@ -6,7 +6,7 @@
;
; CHECK-LABEL: for.body
; CHECK: call void @llvm.prefetch.p0(ptr %scevgep, i32 1, i32 3, i32 1
-; CHECK-not: call void @llvm.prefetch
+; CHECK-NOT: call void @llvm.prefetch
define void @fun(ptr nocapture %Src, ptr nocapture readonly %Dst) {
entry:
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
index 165e73c2e8827..680d9e02a5c5c 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
@@ -406,7 +406,7 @@ for.cond.cleanup:
; CHECK-MID: tB %bb.1
; CHECK-MID: bb.1.while.body:
; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1
-; CHECk-MID: tB %bb.2
+; CHECK-MID: tB %bb.2
; CHECK-MID: bb.2.while.end:
define void @check_negated_xor_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) {
entry:
@@ -440,7 +440,7 @@ while.end:
; CHECK-MID: tB %bb.1
; CHECK-MID: bb.1.while.body:
; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1
-; CHECk-MID: tB %bb.2
+; CHECK-MID: tB %bb.2
; CHECK-MID: bb.2.while.end:
define void @check_negated_cmp_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) {
entry:
@@ -474,7 +474,7 @@ while.end:
; CHECK-MID: tB %bb.1
; CHECK-MID: bb.1.while.body:
; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1
-; CHECk-MID: tB %bb.2
+; CHECK-MID: tB %bb.2
; CHECK-MID: bb.2.while.end:
define void @check_negated_reordered_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) {
entry:
diff --git a/llvm/test/CodeGen/X86/global-sections.ll b/llvm/test/CodeGen/X86/global-sections.ll
index b300fc87e38ab..0175eb23ce080 100644
--- a/llvm/test/CodeGen/X86/global-sections.ll
+++ b/llvm/test/CodeGen/X86/global-sections.ll
@@ -36,8 +36,8 @@ bb5:
}
; LINUX: .size F2,
-; LINUX-NEX: .cfi_endproc
-; LINUX-NEX: .section .rodata,"a", at progbits
+; LINUX-NEXT: .cfi_endproc
+; LINUX-NEXT: .section .rodata,"a", at progbits
; LINUX-SECTIONS: .section .text.F2,"ax", at progbits
; LINUX-SECTIONS: .size F2,
diff --git a/llvm/test/CodeGen/X86/tailregccpic.ll b/llvm/test/CodeGen/X86/tailregccpic.ll
index f89c4ac4df599..a3a17d3b05397 100644
--- a/llvm/test/CodeGen/X86/tailregccpic.ll
+++ b/llvm/test/CodeGen/X86/tailregccpic.ll
@@ -13,12 +13,12 @@ entry:
ret void
}
-;CHECK-LABLE: tail_call_regcall:
+;CHECK-LABEL: tail_call_regcall:
;CHECK: # %bb.0:
;CHECK-NEXT: jmp __regcall3__func # TAILCALL
;CHECK-NEXT: .Lfunc_end0:
-;CHECK-LABLE: __regcall3__func:
+;CHECK-LABEL: __regcall3__func:
;CHECK: addl $_GLOBAL_OFFSET_TABLE_+({{.*}}), %ecx
;CHECK-NEXT: movl a0 at GOT(%ecx), %ecx
;CHECK-NEXT: movl %eax, (%ecx)
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
index d4ed0fba2d7cd..60c3d32595ea5 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
@@ -43,7 +43,7 @@ debugValueSubstitutions:
body: |
bb.0.entry:
successors: %bb.1, %bb.2
- ; CHECK-LABE: bb.0.entry:
+ ; CHECK-LABEL: bb.0.entry:
$rax = MOV64ri 1, debug-instr-number 1, debug-location !17
DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !17
@@ -69,8 +69,8 @@ body: |
;KILL implicit killed $eflags, debug-instr-number 4, debug-location !17
;DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !17
;;; Test non-def operand
- ;; check: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
- ;; check-next: DBG_VALUE_LIST {{.+}}, $noreg
+ ;; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
+ ;; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
$noreg = MOV32ri 1, debug-instr-number 5, debug-location !17
DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !17
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
index 8f43a55b34001..3649b136d3900 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
@@ -55,11 +55,11 @@
## to bb.3, but not into bb.4 because of the intervening out-of-scope block.
## Disabled actual testing of this because it's just for comparison purposes.
#
-# varloc-label: bb.1:
+# varloc-LABEL: bb.1:
# varloc: DBG_VALUE
-# varloc-label: bb.2:
+# varloc-LABEL: bb.2:
## No location here because it's out-of-scope.
-# varloc-label: bb.3:
+# varloc-LABEL: bb.3:
# varloc: DBG_VALUE
#
## Common tail for 'test2' -- this is checking that the assignment of undef or
diff --git a/llvm/test/MC/ARM/coff-relocations.s b/llvm/test/MC/ARM/coff-relocations.s
index 5225b5e656762..16993cf7a8588 100644
--- a/llvm/test/MC/ARM/coff-relocations.s
+++ b/llvm/test/MC/ARM/coff-relocations.s
@@ -25,7 +25,7 @@ branch24t_1:
bl target
@ CHECK-ENCODING-LABEL: <branch24t_1>:
-@ CHECK-ENCODING-NEXR: bl {{.+}} @ imm = #0
+@ CHECK-ENCODING-NEXT: bl {{.+}} @ imm = #0
.thumb_func
branch20t:
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
index e1ba009f3c4c8..9708821affae0 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
@@ -39,7 +39,7 @@
0x04 0x11 0x14 0x9b # CHECK: bal 21104
# The encode/decode functions are not inverses of each other.
0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336
-0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20
+0x18 0x02 0xff 0xfa # CHECK: blezalc $2, -20
# The encode/decode functions are not inverses of each other in the immediate case.
0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336
0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20
@@ -162,13 +162,13 @@
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260
-0x58 0x05 0xff 0xfa # CHECk: blezc $5, -20
+0x58 0x05 0xff 0xfa # CHECK: blezc $5, -20
0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260
0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20
0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260
0x58 0xa5 0xff 0xfa # CHECK: bgezc $5, -20
0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260
-0x5c 0x05 0xff 0xfa # CHECk: bgtzc $5, -20
+0x5c 0x05 0xff 0xfa # CHECK: bgtzc $5, -20
0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260
0x5c 0xa5 0xff 0xfa # CHECK: bltzc $5, -20
0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
index 0030e51d6c238..28cd1619e80ad 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -56,7 +56,7 @@
0x04 0x7e 0xab 0xcd # CHECK: dati $3, $3, 43981
# The encode/decode functions are not inverses of each other in the immediate case.
0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336
-0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20
+0x18 0x02 0xff 0xfa # CHECK: blezalc $2, -20
# The encode/decode functions are not inverses of each other in the immediate case.
0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336
0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20
@@ -181,13 +181,13 @@
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260
-0x58 0x05 0xff 0xfa # CHECk: blezc $5, -20
+0x58 0x05 0xff 0xfa # CHECK: blezc $5, -20
0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260
0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20
0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260
0x58 0xa5 0xff 0xfa # CHECK: bgezc $5, -20
0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260
-0x5c 0x05 0xff 0xfa # CHECk: bgtzc $5, -20
+0x5c 0x05 0xff 0xfa # CHECK: bgtzc $5, -20
0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260
0x5c 0xa5 0xff 0xfa # CHECK: bltzc $5, -20
0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
diff --git a/llvm/test/MC/Mips/expansion-jal-sym-pic.s b/llvm/test/MC/Mips/expansion-jal-sym-pic.s
index c7b5ccc1880bd..1279de10d2503 100644
--- a/llvm/test/MC/Mips/expansion-jal-sym-pic.s
+++ b/llvm/test/MC/Mips/expansion-jal-sym-pic.s
@@ -227,12 +227,12 @@ local_label:
# XO32-NEXT: .reloc ($tmp1), R_MIPS_JALR, weak_label
# ELF-XO32: 3c 19 00 00 lui $25, 0
-# ELF-XO32-MEXT: R_MIPS_CALL_HI16 weak_label
-# ELF-XO32-MEXT: 03 3c c8 21 addu $25, $25, $gp
-# ELF-XO32-MEXT: 8f 39 00 00 lw $25, 0($25)
-# ELF-XO32-MEXT: R_MIPS_CALL_LO16 weak_label
-# ELF-XO32-MEXT: 03 20 f8 09 jalr $25
-# ELF-XO32-MEXT: R_MIPS_JALR weak_label
+# ELF-XO32-NEXT: R_MIPS_CALL_HI16 weak_label
+# ELF-XO32-NEXT: 03 3c c8 21 addu $25, $25, $gp
+# ELF-XO32-NEXT: 8f 39 00 00 lw $25, 0($25)
+# ELF-XO32-NEXT: R_MIPS_CALL_LO16 weak_label
+# ELF-XO32-NEXT: 03 20 f8 09 jalr $25
+# ELF-XO32-NEXT: R_MIPS_JALR weak_label
# N32: lw $25, %call16(weak_label)($gp) # encoding: [0x8f,0x99,A,A]
# N32: # fixup A - offset: 0, value: %call16(weak_label), kind: fixup_Mips_CALL16
diff --git a/llvm/test/MC/Mips/macro-rem.s b/llvm/test/MC/Mips/macro-rem.s
index 40812949664d6..1f10a5392c07f 100644
--- a/llvm/test/MC/Mips/macro-rem.s
+++ b/llvm/test/MC/Mips/macro-rem.s
@@ -95,7 +95,7 @@
# CHECK-NOTRAP: bnez $6, $tmp2 # encoding: [A,A,0xc0,0x14]
# CHECK-NOTRAP: div $zero, $5, $6 # encoding: [0x1a,0x00,0xa6,0x00]
# CHECK-NOTRAP: break 7 # encoding: [0x0d,0x00,0x07,0x00]
-# CHECk-NOTRAP: $tmp2
+# CHECK-NOTRAP: $tmp2
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24]
# CHECK-NOTRAP: bne $6, $1, $tmp3 # encoding: [A,A,0xc1,0x14]
# CHECK-NOTRAP: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
diff --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s
index fd69d37d7cfa0..3280bd2ae3797 100644
--- a/llvm/test/MC/RISCV/zicfiss-valid.s
+++ b/llvm/test/MC/RISCV/zicfiss-valid.s
@@ -44,14 +44,14 @@ sspush x1
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
sspush ra
-# check-asm-and-obj: sspush t0
-# check-asm: encoding: [0x73,0x40,0x50,0xce]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-ASM-AND-OBJ: sspush t0
+# CHECK-ASM: encoding: [0x73,0x40,0x50,0xce]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
sspush x5
-# check-asm-and-obj: sspush t0
-# check-asm: encoding: [0x73,0x40,0x50,0xce]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-ASM-AND-OBJ: sspush t0
+# CHECK-ASM: encoding: [0x73,0x40,0x50,0xce]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
sspush t0
# CHECK-ASM-AND-OBJ: ssrdp ra
diff --git a/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll b/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll
index 2978f85be2385..37fb9fea77044 100644
--- a/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll
+++ b/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll
@@ -39,7 +39,7 @@
; CHECK-DAG: ![[UNALIGNED_UNKNOWN]] = !DIDerivedType(tag: DW_TAG_member, name: "_6",{{.*}}baseType: ![[UNALIGNED_UNKNOWN_BASE:[0-9]+]], size: 9
; CHECK-DAG: ![[UNALIGNED_UNKNOWN_BASE]] = !DICompositeType(tag: DW_TAG_array_type, baseType: ![[UNKNOWN_TYPE_BASE]], size: 16,{{.*}} elements: ![[UNALIGNED_UNKNOWN_ELEMENTS:[0-9]+]])
; CHECK-DAG: ![[UNALIGNED_UNKNOWN_ELEMENTS]] = !{![[UNALIGNED_UNKNOWN_SUBRANGE:[0-9]+]]}
-; CHECk-DAG: ![[UNALIGNED_UNKNOWN_SUBRANGE]] = !DISubrange(count: 2, lowerBound: 0)
+; CHECK-DAG: ![[UNALIGNED_UNKNOWN_SUBRANGE]] = !DISubrange(count: 2, lowerBound: 0)
; CHECK-DAG: ![[STRUCT]] = !DIDerivedType(tag: DW_TAG_member, name: "struct_big_structure_7", scope: ![[FRAME_TYPE]], file: ![[FILE]], line: [[PROMISE_VAR_LINE]], baseType: ![[STRUCT_BASE:[0-9]+]]
; CHECK-DAG: ![[STRUCT_BASE]] = !DICompositeType(tag: DW_TAG_structure_type, name: "struct_big_structure"{{.*}}, align: 64, flags: DIFlagArtificial, elements: ![[STRUCT_ELEMENTS:[0-9]+]]
; CHECK-DAG: ![[STRUCT_ELEMENTS]] = !{![[MEM_TYPE:[0-9]+]]}
diff --git a/llvm/test/Transforms/Inline/update_invoke_prof.ll b/llvm/test/Transforms/Inline/update_invoke_prof.ll
index f6b86dfe5bb1b..b5fb669c93cbd 100644
--- a/llvm/test/Transforms/Inline/update_invoke_prof.ll
+++ b/llvm/test/Transforms/Inline/update_invoke_prof.ll
@@ -66,7 +66,7 @@ ret:
; CHECK: invoke void @callee2(
; CHECK-NEXT: {{.*}} !prof ![[PROF3:[0-9]+]]
-; CHECK-LABL: @callee(
+; CHECK-LABEL: @callee(
; CHECK: invoke void %func(
; CHECK-NEXT: {{.*}} !prof ![[PROF4:[0-9]+]]
; CHECK: invoke void @callee1(
diff --git a/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll b/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll
index e379b32b45734..62573398fc16a 100644
--- a/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll
+++ b/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll
@@ -56,7 +56,7 @@ entry:
call void @llvm.lifetime.start.p0(i64 1, ptr %text)
call void @llvm.lifetime.end.p0(i64 1, ptr %text)
- ; CHECK-NO: call void @llvm.lifetime
+ ; CHECK-NOT: call void @llvm.lifetime
call void @foo(ptr %text) ; Keep alloca alive
diff --git a/llvm/test/Transforms/LoopUnroll/peel-loop2.ll b/llvm/test/Transforms/LoopUnroll/peel-loop2.ll
index a732984d697ad..754e0d32cc1d0 100644
--- a/llvm/test/Transforms/LoopUnroll/peel-loop2.ll
+++ b/llvm/test/Transforms/LoopUnroll/peel-loop2.ll
@@ -32,7 +32,7 @@ for.end:
ret void
}
-; CHECK_LABEL: @funca
+; CHECK-LABEL: @funca
; Peeled iteration
; CHECK: %[[REG1:[0-9]+]] = load i8, ptr @Comma
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll b/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll
index 75f03c7b1a699..c7edf9bdfaf6b 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll
@@ -259,7 +259,7 @@ for.cond.cleanup: ; preds = %for.body
define i4 @test_i4_load(ptr %ddst) {
; CHECK-LABEL: define i4 @test_i4_load
; CHECK-NOT: vector.body:
-; CHECk: ret i4 %{{.*}}
+; CHECK: ret i4 %{{.*}}
;
entry:
br label %for.body
@@ -282,7 +282,7 @@ define i8 @test_load_i8(ptr %ddst) {
; CHECK-LABEL: @test_load_i8(
; CHECK: vector.body:
; CHECK: load <4 x i8>, ptr {{.*}}, align 1, !nontemporal !0
-; CHECk: ret i8 %{{.*}}
+; CHECK: ret i8 %{{.*}}
;
entry:
br label %for.body
@@ -305,7 +305,7 @@ define half @test_half_load(ptr %ddst) {
; CHECK-LABEL: @test_half_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x half>, ptr {{.*}}, align 2, !nontemporal !0
-; CHECk: ret half %{{.*}}
+; CHECK: ret half %{{.*}}
;
entry:
br label %for.body
@@ -328,7 +328,7 @@ define i16 @test_i16_load(ptr %ddst) {
; CHECK-LABEL: @test_i16_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x i16>, ptr {{.*}}, align 2, !nontemporal !0
-; CHECk: ret i16 %{{.*}}
+; CHECK: ret i16 %{{.*}}
;
entry:
br label %for.body
@@ -351,7 +351,7 @@ define i32 @test_i32_load(ptr %ddst) {
; CHECK-LABEL: @test_i32_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x i32>, ptr {{.*}}, align 4, !nontemporal !0
-; CHECk: ret i32 %{{.*}}
+; CHECK: ret i32 %{{.*}}
;
entry:
br label %for.body
@@ -373,7 +373,7 @@ for.cond.cleanup: ; preds = %for.body
define i33 @test_i33_load(ptr %ddst) {
; CHECK-LABEL: @test_i33_load
; CHECK-NOT: vector.body:
-; CHECk: ret i33 %{{.*}}
+; CHECK: ret i33 %{{.*}}
;
entry:
br label %for.body
@@ -395,7 +395,7 @@ for.cond.cleanup: ; preds = %for.body
define i40 @test_i40_load(ptr %ddst) {
; CHECK-LABEL: @test_i40_load
; CHECK-NOT: vector.body:
-; CHECk: ret i40 %{{.*}}
+; CHECK: ret i40 %{{.*}}
;
entry:
br label %for.body
@@ -418,7 +418,7 @@ define i64 @test_i64_load(ptr %ddst) {
; CHECK-LABEL: @test_i64_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x i64>, ptr {{.*}}, align 4, !nontemporal !0
-; CHECk: ret i64 %{{.*}}
+; CHECK: ret i64 %{{.*}}
;
entry:
br label %for.body
@@ -441,7 +441,7 @@ define double @test_double_load(ptr %ddst) {
; CHECK-LABEL: @test_double_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x double>, ptr {{.*}}, align 4, !nontemporal !0
-; CHECk: ret double %{{.*}}
+; CHECK: ret double %{{.*}}
;
entry:
br label %for.body
@@ -464,7 +464,7 @@ define i128 @test_i128_load(ptr %ddst) {
; CHECK-LABEL: @test_i128_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x i128>, ptr {{.*}}, align 4, !nontemporal !0
-; CHECk: ret i128 %{{.*}}
+; CHECK: ret i128 %{{.*}}
;
entry:
br label %for.body
@@ -486,7 +486,7 @@ for.cond.cleanup: ; preds = %for.body
define i256 @test_256_load(ptr %ddst) {
; CHECK-LABEL: @test_256_load
; CHECK-NOT: vector.body:
-; CHECk: ret i256 %{{.*}}
+; CHECK: ret i256 %{{.*}}
;
entry:
br label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/memdep.ll b/llvm/test/Transforms/LoopVectorize/memdep.ll
index b891b4312f18d..eb8c75741c0c0 100644
--- a/llvm/test/Transforms/LoopVectorize/memdep.ll
+++ b/llvm/test/Transforms/LoopVectorize/memdep.ll
@@ -244,7 +244,7 @@ for.end:
; RIGHTVF-LABEL: @pr34283
; RIGHTVF: <4 x i64>
-; WRONGVF-LABLE: @pr34283
+; WRONGVF-LABEL: @pr34283
; WRONGVF-NOT: <8 x i64>
@a = common local_unnamed_addr global [64 x i32] zeroinitializer, align 16
diff --git a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll
index 430baa1cb4f8c..c426737963c52 100644
--- a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll
+++ b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll
@@ -13,7 +13,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12:13"
declare i64 @julia_steprange_last_4949()
define void @"japi1_align!_9477"(ptr %arg) {
-; LV-LAVEL: L26.lver.check
+; LV-LABEL: L26.lver.check
; LV: [[OFMul:%[^ ]*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[Step:%[^ ]*]])
; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 0
; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 1
diff --git a/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll b/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll
index e6c2a7e629a5d..cea752ad6898d 100644
--- a/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll
+++ b/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll
@@ -21,7 +21,7 @@ entry:
define float @f_writeonly(float %val) {
; CHECK-LABEL: @f_writeonly(
-; CHECK-NEXt: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]]
+; CHECK-NEXT: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]]
%res = tail call float @sqrtf(float %val) writeonly
ret float %res
}
diff --git a/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll b/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll
index 5d01e78221e38..3bc18c7cdd7bf 100644
--- a/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll
+++ b/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll
@@ -10,7 +10,7 @@ entry:
if.end: ; preds = %entry
;; Check pseudo probes are next to each other at the beginning of this block.
-; IR-label: if.end
+; IR-LABEL: if.end
; IR: call void @llvm.pseudoprobe(i64 5116412291814990879, i64 1, i32 0, i64 -1)
; IR: call void @llvm.pseudoprobe(i64 5116412291814990879, i64 3, i32 0, i64 -1)
call void @llvm.pseudoprobe(i64 5116412291814990879, i64 1, i32 0, i64 -1)
@@ -19,7 +19,7 @@ if.end: ; preds = %entry
%2 = and i16 %1, 16
%3 = icmp eq i16 %2, 0
;; Check the load-and-cmp sequence is fold into a test instruction.
-; MIR-label: bb.1.if.end
+; MIR-LABEL: bb.1.if.end
; MIR: %[[#REG:]]:gr64 = IMPLICIT_DEF
; MIR: TEST8mi killed %[[#REG]], 1, $noreg, 0, $noreg, 16
; MIR: JCC_1
diff --git a/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll b/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
index bb370a6d1dfeb..7f7790cecb0eb 100644
--- a/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
+++ b/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
@@ -670,7 +670,7 @@ declare void @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1)
define amdgpu_cs void @test_buffer_atomic_fadd(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %offset, i1 %slc) {
; CHECK: immarg operand has non-immediate parameter
; CHECK-NEXT: i1 %slc
- ; CHECK-ENXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
+ ; CHECK-NEXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
ret void
}
diff --git a/llvm/test/tools/llvm-ar/replace-update.test b/llvm/test/tools/llvm-ar/replace-update.test
index c056565f144c5..498febdac0193 100644
--- a/llvm/test/tools/llvm-ar/replace-update.test
+++ b/llvm/test/tools/llvm-ar/replace-update.test
@@ -57,7 +57,7 @@
# MULTIPLE-SYM: symbolnew1
# MULTIPLE-SYM-NEXT: symbol2
-# MULTIPLE-SYM-NEXTs: symbolnew3
+# MULTIPLE-SYM-NEXT: symbolnew3
## Replace newer members with multiple older files:
# RUN: llvm-ar ruU %t/multiple.a %t/1.o %t/2.o
diff --git a/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json b/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json
index ce13fc2ff6e34..33c517da91b5e 100644
--- a/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json
+++ b/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json
@@ -29,7 +29,7 @@ CHECK-SAME: {"branches":{"count":0,"covered":0,"notcovered":0,"percent":0},
CHECK-SAME: "functions":{"count":1,"covered":1,"percent":100},
CHECK-SAME: "instantiations":{"count":1,"covered":1,"percent":100},
CHECK-SAME: "lines":{"count":1,"covered":1,"percent":100},
-CHECk-SAME: "mcdc":{"count":0,"covered":0,"notcovered":0,"percent":0},
+CHECK-SAME: "mcdc":{"count":0,"covered":0,"notcovered":0,"percent":0},
CHECK-SAME: "regions":{"count":1,"covered":1,"notcovered":0,"percent":100}}}
CHECK-SAME: ],
CHECK-SAME: "type":"llvm.coverage.json.export"
diff --git a/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s
index 771bce5023933..37271fb902b4d 100644
--- a/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s
@@ -5,6 +5,6 @@
strd:
strd r0, r1, [r2, +r3]
-@ CHECK-LABEL strd
+@ CHECK-LABEL: strd
@ CHECK: e18200f3 strd r0, r1, [r2, r3]
>From c58ee74e2d7a323a1bd11bf0780f1670c6ca84b2 Mon Sep 17 00:00:00 2001
From: klensy <nightouser at gmail.com>
Date: Wed, 29 May 2024 15:06:29 +0300
Subject: [PATCH 2/5] MC
---
llvm/test/MC/AArch64/SME/feature.s | 2 +-
llvm/test/MC/AArch64/armv8.7a-xs.s | 158 ++++++++---------
llvm/test/MC/AArch64/basic-a64-diagnostics.s | 114 ++++++-------
llvm/test/MC/AMDGPU/hsa-diag-v4.s | 2 +-
llvm/test/MC/ARM/neon-complex.s | 40 ++---
llvm/test/MC/AsmParser/labels.s | 4 +-
llvm/test/MC/COFF/cv-inline-linetable.s | 6 +-
.../MC/Disassembler/AArch64/armv8.6a-bf16.txt | 16 +-
.../MC/Disassembler/AArch64/armv8.7a-xs.txt | 160 +++++++++---------
llvm/test/MC/Disassembler/AArch64/tme.txt | 6 +-
.../MC/Disassembler/AMDGPU/gfx10-wave32.txt | 12 +-
.../MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt | 2 +-
llvm/test/MC/Disassembler/ARM/arm-tests.txt | 2 +-
.../PowerPC/ppc64-encoding-dfp.txt | 2 +-
.../Disassembler/PowerPC/ppc64-encoding.txt | 2 +-
.../Disassembler/PowerPC/ppc64le-encoding.txt | 2 +-
llvm/test/MC/Disassembler/X86/x86-16.txt | 32 ++--
.../MC/LoongArch/Relocations/relax-align.s | 2 +-
llvm/test/MC/MachO/lto-set-conditional.s | 4 +-
llvm/test/MC/Mips/expansion-jal-sym-pic.s | 4 +-
llvm/test/MC/Mips/micromips-dsp/invalid.s | 8 +-
llvm/test/MC/Mips/micromips/valid.s | 4 +-
llvm/test/MC/Mips/mips-pdr-bad.s | 4 +-
llvm/test/MC/Mips/mips32r6/invalid.s | 16 +-
llvm/test/MC/Mips/mips64r6/invalid.s | 16 +-
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s | 26 +--
llvm/test/MC/PowerPC/ppc64-encoding-vmx.s | 4 +-
llvm/test/MC/RISCV/compress-rv64i.s | 4 +-
llvm/test/MC/RISCV/csr-aliases.s | 20 +--
llvm/test/MC/RISCV/relocations.s | 8 +-
llvm/test/MC/WebAssembly/globals.s | 2 +-
llvm/test/MC/X86/apx/evex-format-intel.s | 4 +-
llvm/test/MC/Xtensa/Relocations/relocations.s | 62 +++----
33 files changed, 375 insertions(+), 375 deletions(-)
diff --git a/llvm/test/MC/AArch64/SME/feature.s b/llvm/test/MC/AArch64/SME/feature.s
index f6193b1557b1b..87afb5b333eb5 100644
--- a/llvm/test/MC/AArch64/SME/feature.s
+++ b/llvm/test/MC/AArch64/SME/feature.s
@@ -8,4 +8,4 @@ tbx z0.b, z1.b, z2.b
// Verify +sme flags imply +bf16
bfdot z0.s, z1.h, z2.h
-// CHECK-INST: bfdot z0.s, z1.h, z2.h
+// CHECK: bfdot z0.s, z1.h, z2.h
diff --git a/llvm/test/MC/AArch64/armv8.7a-xs.s b/llvm/test/MC/AArch64/armv8.7a-xs.s
index e3a1e12aae9a5..c41a6f8778263 100644
--- a/llvm/test/MC/AArch64/armv8.7a-xs.s
+++ b/llvm/test/MC/AArch64/armv8.7a-xs.s
@@ -99,39 +99,39 @@
// CHECK: tlbi vale3nxs, x1 // encoding: [0xa1,0x97,0x0e,0xd5]
// CHECK: tlbi vmalls12e1nxs // encoding: [0xdf,0x97,0x0c,0xd5]
// CHECK: tlbi vaale1nxs, x1 // encoding: [0xe1,0x97,0x08,0xd5]
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2E1ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2LE1ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLE1ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE2ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE3ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE1ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE2ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE3ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ASIDE1ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAAE1ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE1ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE1ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE2ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE3ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLS12E1ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAALE1ISnXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2E1nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2LE1nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLE1nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE2nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE3nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE1nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE2nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE3nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ASIDE1nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAAE1nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE1nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE1nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE3nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLS12E1nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAALE1nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI IPAS2E1ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI IPAS2LE1ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VMALLE1ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE2ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE3ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE1ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE2ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE3ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ASIDE1ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAAE1ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE1ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE1ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE2ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE3ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VMALLS12E1ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAALE1ISnXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI IPAS2E1nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI IPAS2LE1nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VMALLE1nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE2nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE3nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE1nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE2nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE3nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ASIDE1nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAAE1nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE1nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE1nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE3nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VMALLS12E1nXS requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAALE1nXS requires: xs
tlbi vmalle1osnxs
tlbi vae1osnxs, x1
@@ -225,49 +225,49 @@
// CHECK: tlbi rvale3isnxs, x1 // encoding: [0xa1,0x92,0x0e,0xd5]
// CHECK: tlbi rvae3osnxs, x1 // encoding: [0x21,0x95,0x0e,0xd5]
// CHECK: tlbi rvale3osnxs, x1 // encoding: [0xa1,0x95,0x0e,0xd5]
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VMALLE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ASIDE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAAE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAALE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI IPAS2E1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI IPAS2LE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE2OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE2OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VMALLS12E1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE3OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE3OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE2OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE3OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VMALLE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VAE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI ASIDE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VAAE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VALE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VAALE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI IPAS2E1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI IPAS2LE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VAE2OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VALE2OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VMALLS12E1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VAE3OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VALE3OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI ALLE2OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI ALLE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI ALLE3OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE1nXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAAE1nXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE1nXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAALE1nXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE1ISnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAAE1ISnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE1ISnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAALE1ISnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAAE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAALE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1ISnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1ISnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1nXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1nXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE2nXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE2nXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE2ISnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE2ISnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE2OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE2OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE3nXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE3nXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE3ISnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE3ISnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE3OSnXS requires: tlb-rmi, xs
+// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE3OSnXS requires: tlb-rmi, xs
diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
index 028700f4d11df..cf13c935ebc18 100644
--- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s
+++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
@@ -87,9 +87,9 @@
// CHECK-ERROR: error: expected compatible register, symbol or integer in range [0, 4095]
// CHECK-ERROR-NEXT: add w4, w5, #-4097
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: expected compatible register, symbol or integer in range [0, 4095]
-// CHECK-ERROR-AARCH64-NEXT: add w5, w6, #0x1000
-// CHECK-ERROR-AARCH64-NEXT: ^
+// CHECK-ERROR-ARM64-NEXT: error: expected compatible register, symbol or integer in range [0, 4095]
+// CHECK-ERROR-ARM64-NEXT: add w5, w6, #0x1000
+// CHECK-ERROR-ARM64-NEXT: ^
// CHECK-ERROR-NEXT: error: expected compatible register, symbol or integer in range [0, 4095]
// CHECK-ERROR-NEXT: add w4, w5, #-4096, lsl #12
// CHECK-ERROR-NEXT: ^
@@ -145,9 +145,9 @@
// Out of range immediate
adds w0, w5, #0x10000
-// CHECK-ERROR-AARCH64: error: expected compatible register, symbol or integer in range [0, 4095]
-// CHECK-ERROR-AARCH64-NEXT: adds w0, w5, #0x10000
-// CHECK-ERROR-AARCH64-NEXT: ^
+// CHECK-ERROR-ARM64: error: expected compatible register, symbol or integer in range [0, 4095]
+// CHECK-ERROR-ARM64-NEXT: adds w0, w5, #0x10000
+// CHECK-ERROR-ARM64-NEXT: ^
// Wn|WSP should be in second place
adds w4, wzr, #0x123
@@ -846,15 +846,15 @@
sxtb x3, x2
sxth xzr, xzr
sxtw x3, x5
-// CHECK-ERROR-AARCH64: error: invalid operand for instruction
-// CHECK-ERROR-AARCH64-NEXT: sxtb x3, x2
-// CHECK-ERROR-AARCH64-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: invalid operand for instruction
-// CHECK-ERROR-AARCH64-NEXT: sxth xzr, xzr
-// CHECK-ERROR-AARCH64-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: invalid operand for instruction
-// CHECK-ERROR-AARCH64-NEXT: sxtw x3, x5
-// CHECK-ERROR-AARCH64-NEXT: ^
+// CHECK-ERROR-ARM64: error: invalid operand for instruction
+// CHECK-ERROR-ARM64-NEXT: sxtb x3, x2
+// CHECK-ERROR-ARM64-NEXT: ^
+// CHECK-ERROR-ARM64-NEXT: error: invalid operand for instruction
+// CHECK-ERROR-ARM64-NEXT: sxth xzr, xzr
+// CHECK-ERROR-ARM64-NEXT: ^
+// CHECK-ERROR-ARM64-NEXT: error: invalid operand for instruction
+// CHECK-ERROR-ARM64-NEXT: sxtw x3, x5
+// CHECK-ERROR-ARM64-NEXT: ^
uxtb x3, x12
uxth x5, x9
@@ -867,9 +867,9 @@
// CHECK-ERROR-NEXT: error: invalid operand for instruction
// CHECK-ERROR-NEXT: uxth x5, x9
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: invalid instruction
-// CHECK-ERROR-AARCH64-NEXT: uxtw x3, x5
-// CHECK-ERROR-AARCH64-NEXT: ^
+// CHECK-ERROR-ARM64-NEXT: error: invalid instruction
+// CHECK-ERROR-ARM64-NEXT: uxtw x3, x5
+// CHECK-ERROR-ARM64-NEXT: ^
// CHECK-ERROR-NEXT: error: invalid operand for instruction
// CHECK-ERROR-NEXT: uxtb x2, sp
// CHECK-ERROR-NEXT: ^
@@ -906,7 +906,7 @@
sbfiz x3, x5, #12, #53
sbfiz sp, x3, #7, #6
sbfiz w3, wsp, #10, #8
-// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31]
+// CHECK-ERROR-ARM64: error: expected integer in range [<lsb>, 31]
// CHECK-ERROR-ARM64: error: expected integer in range [1, 32]
// CHECK-ERROR-NEXT: sbfiz w1, w2, #0, #0
// CHECK-ERROR-NEXT: ^
@@ -940,7 +940,7 @@
sbfx x3, x5, #12, #53
sbfx sp, x3, #7, #6
sbfx w3, wsp, #10, #8
-// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31]
+// CHECK-ERROR-ARM64: error: expected integer in range [<lsb>, 31]
// CHECK-ERROR-ARM64: error: expected integer in range [1, 32]
// CHECK-ERROR-NEXT: sbfx w1, w2, #0, #0
// CHECK-ERROR-NEXT: ^
@@ -974,7 +974,7 @@
bfi x3, x5, #12, #53
bfi sp, x3, #7, #6
bfi w3, wsp, #10, #8
-// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31]
+// CHECK-ERROR-ARM64: error: expected integer in range [<lsb>, 31]
// CHECK-ERROR-ARM64: error: expected integer in range [1, 32]
// CHECK-ERROR-NEXT: bfi w1, w2, #0, #0
// CHECK-ERROR-NEXT: ^
@@ -1008,7 +1008,7 @@
bfxil x3, x5, #12, #53
bfxil sp, x3, #7, #6
bfxil w3, wsp, #10, #8
-// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31]
+// CHECK-ERROR-ARM64: error: expected integer in range [<lsb>, 31]
// CHECK-ERROR-ARM64: error: expected integer in range [1, 32]
// CHECK-ERROR-NEXT: bfxil w1, w2, #0, #0
// CHECK-ERROR-NEXT: ^
@@ -1042,7 +1042,7 @@
ubfiz x3, x5, #12, #53
ubfiz sp, x3, #7, #6
ubfiz w3, wsp, #10, #8
-// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31]
+// CHECK-ERROR-ARM64: error: expected integer in range [<lsb>, 31]
// CHECK-ERROR-ARM64: error: expected integer in range [1, 32]
// CHECK-ERROR-NEXT: ubfiz w1, w2, #0, #0
// CHECK-ERROR-NEXT: ^
@@ -1076,7 +1076,7 @@
ubfx x3, x5, #12, #53
ubfx sp, x3, #7, #6
ubfx w3, wsp, #10, #8
-// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31]
+// CHECK-ERROR-ARM64: error: expected integer in range [<lsb>, 31]
// CHECK-ERROR-ARM64: error: expected integer in range [1, 32]
// CHECK-ERROR-NEXT: ubfx w1, w2, #0, #0
// CHECK-ERROR-NEXT: ^
@@ -1553,7 +1553,7 @@ cbz w1, lsl
//------------------------------------------------------------------------------
fcmp s3, d2
-// CHECK-ERROR-AARCH64: error: expected floating-point constant #0.0
+// CHECK-ERROR-ARM64: error: expected floating-point constant #0.0
// CHECK-ERROR-ARM64: error: invalid operand for instruction
// CHECK-ERROR-NEXT: fcmp s3, d2
// CHECK-ERROR-NEXT: ^
@@ -1847,11 +1847,11 @@ cbz w1, lsl
// CHECK-ERROR: error: expected lane specifier '[1]'
// CHECK-ERROR-NEXT: fmov x3, v0.d[0]
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: lane number incompatible with layout
+// CHECK-ERROR-ARM64-NEXT: error: lane number incompatible with layout
// CHECK-ERROR-ARM64-NEXT: error: invalid operand for instruction
// CHECK-ERROR-NEXT: fmov v29.1d[1], x2
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: lane number incompatible with layout
+// CHECK-ERROR-ARM64-NEXT: error: lane number incompatible with layout
// CHECK-ERROR-ARM64-NEXT: error: expected lane specifier '[1]'
// CHECK-ERROR-NEXT: fmov x7, v0.d[2]
// CHECK-ERROR-NEXT: ^
@@ -1898,7 +1898,7 @@ cbz w1, lsl
stxrb w2, w3, [x4, #20]
stlxrh w10, w11, [w2]
-// CHECK-ERROR-AARCH64: error: expected '#0'
+// CHECK-ERROR-ARM64: error: expected '#0'
// CHECK-ERROR-ARM64: error: index must be absent or #0
// CHECK-ERROR-NEXT: stxrb w2, w3, [x4, #20]
// CHECK-ERROR-NEXT: ^
@@ -2000,13 +2000,13 @@ cbz w1, lsl
ldr x3, [x4, #25], #0
ldr x4, [x9, #0], #4
-// CHECK-ERROR-AARCH64: error: invalid operand for instruction
+// CHECK-ERROR-ARM64: error: invalid operand for instruction
// CHECK-ERROR-ARM64: error: invalid operand for instruction
// CHECK-ERROR-NEXT: ldr x3, [x4, #25], #0
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: expected label or encodable integer pc offset
-// CHECK-ERROR-AARCH64-NEXT: ldr x4, [x9, #0], #4
-// CHECK-ERROR-AARCH64-NEXT: ^
+// CHECK-ERROR-ARM64-NEXT: error: expected label or encodable integer pc offset
+// CHECK-ERROR-ARM64-NEXT: ldr x4, [x9, #0], #4
+// CHECK-ERROR-ARM64-NEXT: ^
strb w1, [x19], #256
strb w9, [sp], #-257
@@ -2438,15 +2438,15 @@ cbz w1, lsl
ldr w0, [x0, #2]
ldrsh w2, [x0, #123]
str q0, [x0, #8]
-// CHECK-ERROR-AARCH64: error: too few operands for instruction
-// CHECK-ERROR-AARCH64-NEXT: ldr w0, [x0, #2]
-// CHECK-ERROR-AARCH64-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction
-// CHECK-ERROR-AARCH64-NEXT: ldrsh w2, [x0, #123]
-// CHECK-ERROR-AARCH64-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction
-// CHECK-ERROR-AARCH64-NEXT: str q0, [x0, #8]
-// CHECK-ERROR-AARCH64-NEXT: ^
+// CHECK-ERROR-ARM64: error: too few operands for instruction
+// CHECK-ERROR-ARM64-NEXT: ldr w0, [x0, #2]
+// CHECK-ERROR-ARM64-NEXT: ^
+// CHECK-ERROR-ARM64-NEXT: error: too few operands for instruction
+// CHECK-ERROR-ARM64-NEXT: ldrsh w2, [x0, #123]
+// CHECK-ERROR-ARM64-NEXT: ^
+// CHECK-ERROR-ARM64-NEXT: error: too few operands for instruction
+// CHECK-ERROR-ARM64-NEXT: str q0, [x0, #8]
+// CHECK-ERROR-ARM64-NEXT: ^
//// 32-bit addresses
ldr w0, [w20]
@@ -2466,12 +2466,12 @@ cbz w1, lsl
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR-NEXT: strb w0, [wsp]
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64: error: invalid operand for instruction
-// CHECK-ERROR-AARCH64-NEXT: strh w31, [x23, #1]
-// CHECK-ERROR-AARCH64-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction
-// CHECK-ERROR-AARCH64-NEXT: str x5, [x22, #12]
-// CHECK-ERROR-AARCH64-NEXT: ^
+// CHECK-ERROR-ARM64: error: invalid operand for instruction
+// CHECK-ERROR-ARM64-NEXT: strh w31, [x23, #1]
+// CHECK-ERROR-ARM64-NEXT: ^
+// CHECK-ERROR-ARM64-NEXT: error: too few operands for instruction
+// CHECK-ERROR-ARM64-NEXT: str x5, [x22, #12]
+// CHECK-ERROR-ARM64-NEXT: ^
// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255]
// CHECK-ERROR-NEXT: str w7, [x12, #16384]
// CHECK-ERROR-NEXT: ^
@@ -2481,18 +2481,18 @@ cbz w1, lsl
prfm #32, [sp, #8]
prfm pldl1strm, [w3, #8]
prfm wibble, [sp]
-// CHECK-ERROR-AARCH64: error: Invalid immediate for instruction
+// CHECK-ERROR-ARM64: error: Invalid immediate for instruction
// CHECK-ERROR-ARM64: error: prefetch operand out of range, [0,31] expected
// CHECK-ERROR-NEXT: prfm #-1, [sp]
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: Invalid immediate for instruction
+// CHECK-ERROR-ARM64-NEXT: error: Invalid immediate for instruction
// CHECK-ERROR-ARM64-NEXT: error: prefetch operand out of range, [0,31] expected
// CHECK-ERROR-NEXT: prfm #32, [sp, #8]
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: invalid operand for instruction
// CHECK-ERROR-NEXT: prfm pldl1strm, [w3, #8]
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: operand specifier not recognised
+// CHECK-ERROR-ARM64-NEXT: error: operand specifier not recognised
// CHECK-ERROR-ARM64-NEXT: error: prefetch hint expected
// CHECK-ERROR-NEXT: prfm wibble, [sp]
// CHECK-ERROR-NEXT: ^
@@ -2600,11 +2600,11 @@ cbz w1, lsl
// CHECK-ERROR-NEXT: error: expected integer shift amount
// CHECK-ERROR-NEXT: ldr q5, [sp, x2, lsl #-1]
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4
+// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4
// CHECK-ERROR-ARM64-NEXT: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4
// CHECK-ERROR-NEXT: ldr q10, [x20, w4, uxtw #2]
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4
+// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4
// CHECK-ERROR-ARM64-NEXT: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4
// CHECK-ERROR-NEXT: str q21, [x20, w4, uxtw #5]
// CHECK-ERROR-NEXT: ^
@@ -3189,11 +3189,11 @@ cbz w1, lsl
// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535]
// CHECK-ERROR-NEXT: movz w4, #65536
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535]
+// CHECK-ERROR-ARM64-NEXT: error: expected relocated symbol or integer in range [0, 65535]
// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0 or 16
// CHECK-ERROR-NEXT: movn w1, #2, lsl #1
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: only 'lsl #+N' valid after immediate
+// CHECK-ERROR-ARM64-NEXT: error: only 'lsl #+N' valid after immediate
// CHECK-ERROR-ARM64-NEXT: error: expected integer shift amount
// CHECK-ERROR-NEXT: movk w3, #0, lsl #-1
// CHECK-ERROR-NEXT: ^
@@ -3203,11 +3203,11 @@ cbz w1, lsl
// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535]
// CHECK-ERROR-NEXT: movz x3, #-1
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535]
+// CHECK-ERROR-ARM64-NEXT: error: expected relocated symbol or integer in range [0, 65535]
// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0 or 16
// CHECK-ERROR-NEXT: movk w3, #1, lsl #32
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535]
+// CHECK-ERROR-ARM64-NEXT: error: expected relocated symbol or integer in range [0, 65535]
// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0, 16, 32 or 48
// CHECK-ERROR-NEXT: movn x2, #12, lsl #64
// CHECK-ERROR-NEXT: ^
@@ -3429,7 +3429,7 @@ cbz w1, lsl
// CHECK-ERROR-NEXT: error: specified {{IC|ic}} op does not use a register
// CHECK-ERROR-NEXT: ic ialluis, x2
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-AARCH64-NEXT: error: operand specifier not recognised
+// CHECK-ERROR-ARM64-NEXT: error: operand specifier not recognised
// CHECK-ERROR-ARM64-NEXT: error: invalid operand for IC instruction
// CHECK-ERROR-NEXT: ic allu, x7
// CHECK-ERROR-NEXT: ^
diff --git a/llvm/test/MC/AMDGPU/hsa-diag-v4.s b/llvm/test/MC/AMDGPU/hsa-diag-v4.s
index 069b71b7229cd..cc10d3400e9b1 100644
--- a/llvm/test/MC/AMDGPU/hsa-diag-v4.s
+++ b/llvm/test/MC/AMDGPU/hsa-diag-v4.s
@@ -54,7 +54,7 @@
// GCN-LABEL: warning: test_amdhsa_group_segment_fixed_size_repeated
// AMDHSA: error: .amdhsa_ directives cannot be repeated
-// NONAMDHSA-: error: unknown directive
+// NONAMDHSA: error: unknown directive
.warning "test_amdhsa_group_segment_fixed_size_repeated"
.amdhsa_kernel test_amdhsa_group_segment_fixed_size_repeated
.amdhsa_group_segment_fixed_size 1
diff --git a/llvm/test/MC/ARM/neon-complex.s b/llvm/test/MC/ARM/neon-complex.s
index 6054a08dc82e8..50efb23f003f8 100644
--- a/llvm/test/MC/ARM/neon-complex.s
+++ b/llvm/test/MC/ARM/neon-complex.s
@@ -24,7 +24,7 @@
// FP16-THUMB: vcmla.f16 d0, d1, d2, #0 @ encoding: [0x21,0xfc,0x02,0x08]
// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float
// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
vcmla.f16 q0, q1, q2, #0
// FP16-ARM: vcmla.f16 q0, q1, q2, #0 @ encoding: [0x44,0x08,0x22,0xfc]
// FP16-THUMB: vcmla.f16 q0, q1, q2, #0 @ encoding: [0x22,0xfc,0x44,0x08]
@@ -32,36 +32,36 @@
// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: invalid instruction, any one of the following would fix this:
// V82A: :[[@LINE-5]]:{{[0-9]*}}: note: instruction requires: mve.fp
// V82A: :[[@LINE-6]]:{{[0-9]*}}: note: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-7]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-7]]:{{[0-9]*}}: error: instruction requires: NEON
vcmla.f32 d0, d1, d2, #0
// ARM: vcmla.f32 d0, d1, d2, #0 @ encoding: [0x02,0x08,0x31,0xfc]
// THUMB: vcmla.f32 d0, d1, d2, #0 @ encoding: [0x31,0xfc,0x02,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
vcmla.f32 q0, q1, q2, #0
// ARM: vcmla.f32 q0, q1, q2, #0 @ encoding: [0x44,0x08,0x32,0xfc]
// THUMB: vcmla.f32 q0, q1, q2, #0 @ encoding: [0x32,0xfc,0x44,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: invalid instruction, any one of the following would fix this:
// V82A: :[[@LINE-4]]:{{[0-9]*}}: note: instruction requires: mve.fp
// V82A: :[[@LINE-5]]:{{[0-9]*}}: note: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-6]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-6]]:{{[0-9]*}}: error: instruction requires: NEON
// Valid rotations
vcmla.f32 d0, d1, d2, #90
// ARM: vcmla.f32 d0, d1, d2, #90 @ encoding: [0x02,0x08,0xb1,0xfc]
// THUMB: vcmla.f32 d0, d1, d2, #90 @ encoding: [0xb1,0xfc,0x02,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
vcmla.f32 d0, d1, d2, #180
// ARM: vcmla.f32 d0, d1, d2, #180 @ encoding: [0x02,0x08,0x31,0xfd]
// THUMB: vcmla.f32 d0, d1, d2, #180 @ encoding: [0x31,0xfd,0x02,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
vcmla.f32 d0, d1, d2, #270
// ARM: vcmla.f32 d0, d1, d2, #270 @ encoding: [0x02,0x08,0xb1,0xfd]
// THUMB: vcmla.f32 d0, d1, d2, #270 @ encoding: [0xb1,0xfd,0x02,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
// Invalid rotations
vcmla.f32 d0, d1, d2, #-90
@@ -82,7 +82,7 @@
// FP16-THUMB: vcadd.f16 d0, d1, d2, #90 @ encoding: [0x81,0xfc,0x02,0x08]
// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float
// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
vcadd.f16 q0, q1, q2, #90
// FP16-ARM: vcadd.f16 q0, q1, q2, #90 @ encoding: [0x44,0x08,0x82,0xfc]
// FP16-THUMB: vcadd.f16 q0, q1, q2, #90 @ encoding: [0x82,0xfc,0x44,0x08]
@@ -90,26 +90,26 @@
// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: invalid instruction, any one of the following would fix this:
// V82A: :[[@LINE-5]]:{{[0-9]*}}: note: instruction requires: mve.fp
// V82A: :[[@LINE-6]]:{{[0-9]*}}: note: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-7]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-7]]:{{[0-9]*}}: error: instruction requires: NEON
vcadd.f32 d0, d1, d2, #90
// ARM: vcadd.f32 d0, d1, d2, #90 @ encoding: [0x02,0x08,0x91,0xfc]
// THUMB: vcadd.f32 d0, d1, d2, #90 @ encoding: [0x91,0xfc,0x02,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
vcadd.f32 q0, q1, q2, #90
// ARM: vcadd.f32 q0, q1, q2, #90 @ encoding: [0x44,0x08,0x92,0xfc]
// THUMB: vcadd.f32 q0, q1, q2, #90 @ encoding: [0x92,0xfc,0x44,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: invalid instruction, any one of the following would fix this:
// V82A: :[[@LINE-4]]:{{[0-9]*}}: note: instruction requires: mve.fp
// V82A: :[[@LINE-5]]:{{[0-9]*}}: note: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-6]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-6]]:{{[0-9]*}}: error: instruction requires: NEON
// Valid rotations
vcadd.f32 d0, d1, d2, #270
// ARM: vcadd.f32 d0, d1, d2, #270 @ encoding: [0x02,0x08,0x91,0xfd]
// THUMB: vcadd.f32 d0, d1, d2, #270 @ encoding: [0x91,0xfd,0x02,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
// Invalid rotations
vcadd.f32 d0, d1, d2, #0
@@ -137,40 +137,40 @@
// FP16-THUMB: vcmla.f16 d0, d1, d2[0], #0 @ encoding: [0x01,0xfe,0x02,0x08]
// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float
// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
vcmla.f16 q0, q1, d2[0], #0
// FP16-ARM: vcmla.f16 q0, q1, d2[0], #0 @ encoding: [0x42,0x08,0x02,0xfe]
// FP16-THUMB: vcmla.f16 q0, q1, d2[0], #0 @ encoding: [0x02,0xfe,0x42,0x08]
// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float
// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
vcmla.f32 d0, d1, d2[0], #0
// ARM: vcmla.f32 d0, d1, d2[0], #0 @ encoding: [0x02,0x08,0x81,0xfe]
// THUMB: vcmla.f32 d0, d1, d2[0], #0 @ encoding: [0x81,0xfe,0x02,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
vcmla.f32 q0, q1, d2[0], #0
// ARM: vcmla.f32 q0, q1, d2[0], #0 @ encoding: [0x42,0x08,0x82,0xfe]
// THUMB: vcmla.f32 q0, q1, d2[0], #0 @ encoding: [0x82,0xfe,0x42,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON
// Valid rotations
vcmla.f32 d0, d1, d2[0], #90
// ARM: vcmla.f32 d0, d1, d2[0], #90 @ encoding: [0x02,0x08,0x91,0xfe]
// THUMB: vcmla.f32 d0, d1, d2[0], #90 @ encoding: [0x91,0xfe,0x02,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
vcmla.f32 d0, d1, d2[0], #180
// ARM: vcmla.f32 d0, d1, d2[0], #180 @ encoding: [0x02,0x08,0xa1,0xfe]
// THUMB: vcmla.f32 d0, d1, d2[0], #180 @ encoding: [0xa1,0xfe,0x02,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
vcmla.f32 d0, d1, d2[0], #270
// ARM: vcmla.f32 d0, d1, d2[0], #270 @ encoding: [0x02,0x08,0xb1,0xfe]
// THUMB: vcmla.f32 d0, d1, d2[0], #270 @ encoding: [0xb1,0xfe,0x02,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
// Invalid rotations
vcmla.f32 d0, d1, d2[0], #-90
@@ -188,7 +188,7 @@
// FP16-ARM: vcmla.f16 d0, d1, d2[1], #0 @ encoding: [0x22,0x08,0x01,0xfe]
// FP16-THUMB: vcmla.f16 d0, d1, d2[1], #0 @ encoding: [0x01,0xfe,0x22,0x08]
// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
-// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
+// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON
// Invalid indices
// The text of these errors vary depending on whether fullfp16 is present.
diff --git a/llvm/test/MC/AsmParser/labels.s b/llvm/test/MC/AsmParser/labels.s
index 599ce72c44eef..5062f4f99641c 100644
--- a/llvm/test/MC/AsmParser/labels.s
+++ b/llvm/test/MC/AsmParser/labels.s
@@ -29,7 +29,7 @@ foo:
// CHECK: .long 11
.long "a 0"
-// XXCHCK: .section "a 1,a 2"
+// CHECK: .section "a 1,a 2"
//.section "a 1", "a 2"
// CHECK: .globl "a 3"
@@ -46,7 +46,7 @@ foo:
// FIXME: We don't bother to support .lsym.
-// CHECX: .lsym "a 8",1
+// COM: CHECK: .lsym "a 8",1
// .lsym "a 8", 1
// CHECK: .set "a 9", a-b
diff --git a/llvm/test/MC/COFF/cv-inline-linetable.s b/llvm/test/MC/COFF/cv-inline-linetable.s
index 2748fa71df75c..4cea3b1576896 100644
--- a/llvm/test/MC/COFF/cv-inline-linetable.s
+++ b/llvm/test/MC/COFF/cv-inline-linetable.s
@@ -76,9 +76,9 @@ Lfunc_end0:
# PDB-NEXT: 0B26 code 0x1F (+0x6) line 2 (+1)
# PDB-NEXT: 0B27 code 0x26 (+0x7) line 3 (+1)
# PDB-NEXT: 0407 code end 0x2D (+0x7)
-# PEB: S_INLINESITE_END
-# PEB: S_INLINESITE_END
-# PEB: S_PROC_ID_END
+# PDB: S_INLINESITE_END
+# PDB: S_INLINESITE_END
+# PDB: S_PROC_ID_END
.section .debug$T,"dr"
.long 4
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt b/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt
index 1d37bbcaf3865..ebaeeba50d10f 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt
@@ -22,13 +22,13 @@
# CHECK: bfdot v2.4s, v3.8h, v4.2h[2]
# CHECK: bfdot v2.4s, v3.8h, v4.2h[3]
# NOBF16: warning: invalid instruction encoding
-# NOBF-NEXT: [0x62,0xf0,0x44,0x4f]
+# NOBF16-NEXT: [0x62,0xf0,0x44,0x4f]
# NOBF16: warning: invalid instruction encoding
-# NOBF6-NEXT: [0x62,0xf0,0x64,0x4f]
+# NOBF16-NEXT: [0x62,0xf0,0x64,0x4f]
# NOBF16: warning: invalid instruction encoding
-# NOBF6-NEXT: [0x62,0xf8,0x44,0x4f]
+# NOBF16-NEXT: [0x62,0xf8,0x44,0x4f]
# NOBF16: warning: invalid instruction encoding
-# NOBF6-NEXT: [0x62,0xf8,0x64,0x4f]
+# NOBF16-NEXT: [0x62,0xf8,0x64,0x4f]
[0x62,0xf0,0x44,0x0f]
@@ -40,13 +40,13 @@
# CHECK: bfdot v2.2s, v3.4h, v4.2h[2]
# CHECK: bfdot v2.2s, v3.4h, v4.2h[3]
# NOBF16: warning: invalid instruction encoding
-# NOBF-NEXT: [0x62,0xf0,0x44,0x0f]
+# NOBF16-NEXT: [0x62,0xf0,0x44,0x0f]
# NOBF16: warning: invalid instruction encoding
-# NOBF6-NEXT: [0x62,0xf0,0x64,0x0f]
+# NOBF16-NEXT: [0x62,0xf0,0x64,0x0f]
# NOBF16: warning: invalid instruction encoding
-# NOBF6-NEXT: [0x62,0xf8,0x44,0x0f]
+# NOBF16-NEXT: [0x62,0xf8,0x44,0x0f]
# NOBF16: warning: invalid instruction encoding
-# NOBF6-NEXT: [0x62,0xf8,0x64,0x0f]
+# NOBF16-NEXT: [0x62,0xf8,0x64,0x0f]
[0x62,0xec,0x44,0x6e]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
index ce09954f5f0f8..042cd5b9c89e7 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
@@ -89,38 +89,38 @@
# CHECK: tlbi vale3nxs, x1
# CHECK: tlbi vmalls12e1nxs
# CHECK: tlbi vaale1nxs, x1
-# CHECK_NO_XS: sys #4, c9, c0, #1, x1
-# CHECK_NO_XS: sys #4, c9, c0, #5, x1
-# CHECK_NO_XS: sys #0, c9, c3, #0
-# CHECK_NO_XS: sys #4, c9, c3, #0
-# CHECK_NO_XS: sys #6, c9, c3, #0
-# CHECK_NO_XS: sys #0, c9, c3, #1, x1
-# CHECK_NO_XS: sys #4, c9, c3, #1, x1
-# CHECK_NO_XS: sys #6, c9, c3, #1, x1
-# CHECK_NO_XS: sys #0, c9, c3, #2, x1
-# CHECK_NO_XS: sys #0, c9, c3, #3, x1
-# CHECK_NO_XS: sys #4, c9, c3, #4
-# CHECK_NO_XS: sys #0, c9, c3, #5, x1
-# CHECK_NO_XS: sys #4, c9, c3, #5, x1
-# CHECK_NO_XS: sys #6, c9, c3, #5, x1
-# CHECK_NO_XS: sys #4, c9, c3, #6
-# CHECK_NO_XS: sys #0, c9, c3, #7, x1
-# CHECK_NO_XS: sys #4, c9, c4, #1, x1
-# CHECK_NO_XS: sys #4, c9, c4, #5, x1
-# CHECK_NO_XS: sys #0, c9, c7, #0
-# CHECK_NO_XS: sys #4, c9, c7, #0
-# CHECK_NO_XS: sys #6, c9, c7, #0
-# CHECK_NO_XS: sys #0, c9, c7, #1, x1
-# CHECK_NO_XS: sys #4, c9, c7, #1, x1
-# CHECK_NO_XS: sys #6, c9, c7, #1, x1
-# CHECK_NO_XS: sys #0, c9, c7, #2, x1
-# CHECK_NO_XS: sys #0, c9, c7, #3, x1
-# CHECK_NO_XS: sys #4, c9, c7, #4
-# CHECK_NO_XS: sys #0, c9, c7, #5, x1
-# CHECK_NO_XS: sys #4, c9, c7, #5, x1
-# CHECK_NO_XS: sys #6, c9, c7, #5, x1
-# CHECK_NO_XS: sys #4, c9, c7, #6
-# CHECK_NO_XS: sys #0, c9, c7, #7, x1
+# CHECK-NO-XS: sys #4, c9, c0, #1, x1
+# CHECK-NO-XS: sys #4, c9, c0, #5, x1
+# CHECK-NO-XS: sys #0, c9, c3, #0
+# CHECK-NO-XS: sys #4, c9, c3, #0
+# CHECK-NO-XS: sys #6, c9, c3, #0
+# CHECK-NO-XS: sys #0, c9, c3, #1, x1
+# CHECK-NO-XS: sys #4, c9, c3, #1, x1
+# CHECK-NO-XS: sys #6, c9, c3, #1, x1
+# CHECK-NO-XS: sys #0, c9, c3, #2, x1
+# CHECK-NO-XS: sys #0, c9, c3, #3, x1
+# CHECK-NO-XS: sys #4, c9, c3, #4
+# CHECK-NO-XS: sys #0, c9, c3, #5, x1
+# CHECK-NO-XS: sys #4, c9, c3, #5, x1
+# CHECK-NO-XS: sys #6, c9, c3, #5, x1
+# CHECK-NO-XS: sys #4, c9, c3, #6
+# CHECK-NO-XS: sys #0, c9, c3, #7, x1
+# CHECK-NO-XS: sys #4, c9, c4, #1, x1
+# CHECK-NO-XS: sys #4, c9, c4, #5, x1
+# CHECK-NO-XS: sys #0, c9, c7, #0
+# CHECK-NO-XS: sys #4, c9, c7, #0
+# CHECK-NO-XS: sys #6, c9, c7, #0
+# CHECK-NO-XS: sys #0, c9, c7, #1, x1
+# CHECK-NO-XS: sys #4, c9, c7, #1, x1
+# CHECK-NO-XS: sys #6, c9, c7, #1, x1
+# CHECK-NO-XS: sys #0, c9, c7, #2, x1
+# CHECK-NO-XS: sys #0, c9, c7, #3, x1
+# CHECK-NO-XS: sys #4, c9, c7, #4
+# CHECK-NO-XS: sys #0, c9, c7, #5, x1
+# CHECK-NO-XS: sys #4, c9, c7, #5, x1
+# CHECK-NO-XS: sys #6, c9, c7, #5, x1
+# CHECK-NO-XS: sys #4, c9, c7, #6
+# CHECK-NO-XS: sys #0, c9, c7, #7, x1
[0x1f,0x91,0x08,0xd5]
[0x21,0x91,0x08,0xd5]
@@ -214,51 +214,51 @@
# CHECK: tlbi rvale3isnxs, x1
# CHECK: tlbi rvae3osnxs, x1
# CHECK: tlbi rvale3osnxs, x1
-# CHECK_NO_XS: sys #0, c9, c1, #0
-# CHECK_NO_XS: sys #0, c9, c1, #1, x1
-# CHECK_NO_XS: sys #0, c9, c1, #2, x1
-# CHECK_NO_XS: sys #0, c9, c1, #3, x1
-# CHECK_NO_XS: sys #0, c9, c1, #5, x1
-# CHECK_NO_XS: sys #0, c9, c1, #7, x1
-# CHECK_NO_XS: sys #4, c9, c4, #0, x1
-# CHECK_NO_XS: sys #4, c9, c4, #4, x1
-# CHECK_NO_XS: sys #4, c9, c1, #1, x1
-# CHECK_NO_XS: sys #4, c9, c1, #5, x1
-# CHECK_NO_XS: sys #4, c9, c1, #6
-# CHECK_NO_XS: sys #6, c9, c1, #1, x1
-# CHECK_NO_XS: sys #6, c9, c1, #5, x1
-# CHECK_NO_XS: sys #4, c9, c1, #0
-# CHECK_NO_XS: sys #4, c9, c1, #4
-# CHECK_NO_XS: sys #6, c9, c1, #0
-# CHECK_NO_XS: sys #0, c9, c6, #1, x1
-# CHECK_NO_XS: sys #0, c9, c6, #3, x1
-# CHECK_NO_XS: sys #0, c9, c6, #5, x1
-# CHECK_NO_XS: sys #0, c9, c6, #7, x1
-# CHECK_NO_XS: sys #0, c9, c2, #1, x1
-# CHECK_NO_XS: sys #0, c9, c2, #3, x1
-# CHECK_NO_XS: sys #0, c9, c2, #5, x1
-# CHECK_NO_XS: sys #0, c9, c2, #7, x1
-# CHECK_NO_XS: sys #0, c9, c5, #1, x1
-# CHECK_NO_XS: sys #0, c9, c5, #3, x1
-# CHECK_NO_XS: sys #0, c9, c5, #5, x1
-# CHECK_NO_XS: sys #0, c9, c5, #7, x1
-# CHECK_NO_XS: sys #4, c9, c0, #2, x1
-# CHECK_NO_XS: sys #4, c9, c0, #6, x1
-# CHECK_NO_XS: sys #4, c9, c4, #2, x1
-# CHECK_NO_XS: sys #4, c9, c4, #6, x1
-# CHECK_NO_XS: sys #4, c9, c4, #3, x1
-# CHECK_NO_XS: sys #4, c9, c4, #7, x1
-# CHECK_NO_XS: sys #4, c9, c6, #1, x1
-# CHECK_NO_XS: sys #4, c9, c6, #5, x1
-# CHECK_NO_XS: sys #4, c9, c2, #1, x1
-# CHECK_NO_XS: sys #4, c9, c2, #5, x1
-# CHECK_NO_XS: sys #4, c9, c5, #1, x1
-# CHECK_NO_XS: sys #4, c9, c5, #5, x1
-# CHECK_NO_XS: sys #6, c9, c6, #1, x1
-# CHECK_NO_XS: sys #6, c9, c6, #5, x1
-# CHECK_NO_XS: sys #6, c9, c2, #1, x1
-# CHECK_NO_XS: sys #6, c9, c2, #5, x1
-# CHECK_NO_XS: sys #6, c9, c5, #1, x1
-# CHECK_NO_XS: sys #6, c9, c5, #5, x1
-# CHECK_NO_XS: sys #0, c9, c1, #0
-# CHECK_NO_XS: sys #4, c9, c0, #1, x1
+# CHECK-NO-XS: sys #0, c9, c1, #0
+# CHECK-NO-XS: sys #0, c9, c1, #1, x1
+# CHECK-NO-XS: sys #0, c9, c1, #2, x1
+# CHECK-NO-XS: sys #0, c9, c1, #3, x1
+# CHECK-NO-XS: sys #0, c9, c1, #5, x1
+# CHECK-NO-XS: sys #0, c9, c1, #7, x1
+# CHECK-NO-XS: sys #4, c9, c4, #0, x1
+# CHECK-NO-XS: sys #4, c9, c4, #4, x1
+# CHECK-NO-XS: sys #4, c9, c1, #1, x1
+# CHECK-NO-XS: sys #4, c9, c1, #5, x1
+# CHECK-NO-XS: sys #4, c9, c1, #6
+# CHECK-NO-XS: sys #6, c9, c1, #1, x1
+# CHECK-NO-XS: sys #6, c9, c1, #5, x1
+# CHECK-NO-XS: sys #4, c9, c1, #0
+# CHECK-NO-XS: sys #4, c9, c1, #4
+# CHECK-NO-XS: sys #6, c9, c1, #0
+# CHECK-NO-XS: sys #0, c9, c6, #1, x1
+# CHECK-NO-XS: sys #0, c9, c6, #3, x1
+# CHECK-NO-XS: sys #0, c9, c6, #5, x1
+# CHECK-NO-XS: sys #0, c9, c6, #7, x1
+# CHECK-NO-XS: sys #0, c9, c2, #1, x1
+# CHECK-NO-XS: sys #0, c9, c2, #3, x1
+# CHECK-NO-XS: sys #0, c9, c2, #5, x1
+# CHECK-NO-XS: sys #0, c9, c2, #7, x1
+# CHECK-NO-XS: sys #0, c9, c5, #1, x1
+# CHECK-NO-XS: sys #0, c9, c5, #3, x1
+# CHECK-NO-XS: sys #0, c9, c5, #5, x1
+# CHECK-NO-XS: sys #0, c9, c5, #7, x1
+# CHECK-NO-XS: sys #4, c9, c0, #2, x1
+# CHECK-NO-XS: sys #4, c9, c0, #6, x1
+# CHECK-NO-XS: sys #4, c9, c4, #2, x1
+# CHECK-NO-XS: sys #4, c9, c4, #6, x1
+# CHECK-NO-XS: sys #4, c9, c4, #3, x1
+# CHECK-NO-XS: sys #4, c9, c4, #7, x1
+# CHECK-NO-XS: sys #4, c9, c6, #1, x1
+# CHECK-NO-XS: sys #4, c9, c6, #5, x1
+# CHECK-NO-XS: sys #4, c9, c2, #1, x1
+# CHECK-NO-XS: sys #4, c9, c2, #5, x1
+# CHECK-NO-XS: sys #4, c9, c5, #1, x1
+# CHECK-NO-XS: sys #4, c9, c5, #5, x1
+# CHECK-NO-XS: sys #6, c9, c6, #1, x1
+# CHECK-NO-XS: sys #6, c9, c6, #5, x1
+# CHECK-NO-XS: sys #6, c9, c2, #1, x1
+# CHECK-NO-XS: sys #6, c9, c2, #5, x1
+# CHECK-NO-XS: sys #6, c9, c5, #1, x1
+# CHECK-NO-XS: sys #6, c9, c5, #5, x1
+# CHECK-NO-XS: sys #0, c9, c1, #0
+# CHECK-NO-XS: sys #4, c9, c0, #1, x1
diff --git a/llvm/test/MC/Disassembler/AArch64/tme.txt b/llvm/test/MC/Disassembler/AArch64/tme.txt
index f250b33e0e1df..3c3d5c1f6ff9a 100644
--- a/llvm/test/MC/Disassembler/AArch64/tme.txt
+++ b/llvm/test/MC/Disassembler/AArch64/tme.txt
@@ -12,8 +12,8 @@
# CHECK: tcommit
# CHECK: tcancel #0x1234
-# NOTEME: mrs
-# NOTEME-NEXT: mrs
-# NOTEME-NEXT: msr
+# NOTME: mrs
+# NOTME-NEXT: mrs
+# NOTME-NEXT: msr
# NOTME: warning: invalid instruction encoding
# NOTME-NEXT: [0x80,0x46,0x62,0xd4]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10-wave32.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10-wave32.txt
index 7d15f041bd770..78ca1bbdacf29 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10-wave32.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10-wave32.txt
@@ -91,20 +91,20 @@
# FIXME: Results in invalid v_subrev_u16_dpp which apparently has the same encoding but does not exist in GFX10
-# gfx1032: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-# gfx1064: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+# COM: GFX1032: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+# COM: GFX1064: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
# 0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x00
# FIXME: Results in v_mul_lo_u16_dpp
-# gfx1032: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-# gfx1064: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+# COM: GFX1032: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+# COM: GFX1064: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
# 0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x00
# FIXME: gives v_lshlrev_b16_dpp
-# gfx1032: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-# gfx1064: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+# COM: GFX1032: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+# COM: GFX1064: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
# 0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00
# GFX1032: v_add_co_u32 v0, s0, v0, v2
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
index 36c58d4c67326..473ede00603a7 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
@@ -1674,7 +1674,7 @@
# GFX12: ds_pk_add_f16 v0, v0 offset:4660 ; encoding: [0x34,0x12,0x68,0xda,0x00,0x00,0x00,0x00]
0x34,0x12,0x68,0xda,0x00,0x00,0x00,0x00
-# gfx12: ds_pk_add_bf16 v2, v1 ; encoding: [0x00,0x00,0x6c,0xda,0x02,0x01,0x00,0x00]
+# GFX12: ds_pk_add_bf16 v2, v1 ; encoding: [0x00,0x00,0x6c,0xda,0x02,0x01,0x00,0x00]
0x00,0x00,0x6c,0xda,0x02,0x01,0x00,0x00
# GFX12: ds_pk_add_f16 v0, v0 offset:4660 ; encoding: [0x34,0x12,0x68,0xda,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/ARM/arm-tests.txt b/llvm/test/MC/Disassembler/ARM/arm-tests.txt
index 008bb1154e57f..fb999c3349c79 100644
--- a/llvm/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/llvm/test/MC/Disassembler/ARM/arm-tests.txt
@@ -48,7 +48,7 @@
# FIXME: LDC encoding information is incorrect. Re-enable this along with more
# robust testing for other values when we get it fleshed out and working
# properly.
-# CHECKx: ldclvc p5, cr15, [r8], #-0
+# COM: CHECK: ldclvc p5, cr15, [r8], #-0
#0x00 0xf5 0x78 0x7c
# CHECK: ldc p13, c9, [r2, #0]!
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
index 91831b64d4472..9ed3ac5a8fb9d 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
@@ -156,7 +156,7 @@
# CHECK: dcffixq. 12, 8
0xfd 0x80 0x46 0x45
-# CHECK : dcffixqq 18, 20
+# CHECK: dcffixqq 18, 20
0xfe 0x40 0xa7 0xc4
# CHECK: dctfix 8, 4
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
index 567c4fa5bd5ab..54bf5c4da43c0 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
@@ -325,7 +325,7 @@
# CHECK: subfeo 2, 3, 4
0x7c 0x43 0x25 0x10
-# CHECKE: subfeo. 2, 3, 4
+# CHECK: subfeo. 2, 3, 4
0x7c 0x43 0x25 0x11
# CHECK: addme 2, 3
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
index 15427e91a5b2a..269b561c91bf4 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
@@ -313,7 +313,7 @@
# CHECK: subfeo 2, 3, 4
0x10 0x25 0x43 0x7c
-# CHECKE: subfeo. 2, 3, 4
+# CHECK: subfeo. 2, 3, 4
0x11 0x25 0x43 0x7c
# CHECK: addme 2, 3
diff --git a/llvm/test/MC/Disassembler/X86/x86-16.txt b/llvm/test/MC/Disassembler/X86/x86-16.txt
index 7de31411885ce..df91cd0d5bcd9 100644
--- a/llvm/test/MC/Disassembler/X86/x86-16.txt
+++ b/llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -222,46 +222,46 @@
# CHECK: movw (%eax), %cs
0x67 0x8e 0x08
-# CHECKX: movl %cr0, %eax
+# CHECK: movl %cr0, %eax
0x0f 0x20 0xc0
-# CHECKX: movl %cr1, %eax
+# CHECK: movl %cr1, %eax
0x0f 0x20 0xc8
-# CHECKX: movl %cr2, %eax
+# CHECK: movl %cr2, %eax
0x0f 0x20 0xd0
-# CHECKX: movl %cr3, %eax
+# CHECK: movl %cr3, %eax
0x0f 0x20 0xd8
-# CHECKX: movl %cr4, %eax
+# CHECK: movl %cr4, %eax
0x0f 0x20 0xe0
-# CHECKX: movl %dr0, %eax
+# CHECK: movl %dr0, %eax
0x0f 0x21 0xc0
-# CHECKX: movl %dr1, %eax
+# CHECK: movl %dr1, %eax
0x0f 0x21 0xc8
-# CHECKX: movl %dr1, %eax
+# CHECK: movl %dr1, %eax
0x0f 0x21 0xc8
-# CHECKX: movl %dr2, %eax
+# CHECK: movl %dr2, %eax
0x0f 0x21 0xd0
-# CHECKX: movl %dr3, %eax
+# CHECK: movl %dr3, %eax
0x0f 0x21 0xd8
-# CHECKX: movl %dr4, %eax
+# CHECK: movl %dr4, %eax
0x0f 0x21 0xe0
-# CHECKX: movl %dr5, %eax
+# CHECK: movl %dr5, %eax
0x0f 0x21 0xe8
-# CHECKX: movl %dr6, %eax
+# CHECK: movl %dr6, %eax
0x0f 0x21 0xf0
-# CHECKX: movl %dr7, %eax
+# CHECK: movl %dr7, %eax
0x0f 0x21 0xf8
# CHECK: wait
@@ -765,10 +765,10 @@
# CHECK: fsubp %st, %st(2)
0xde 0xe2
-# CHECKX: nop
+# CHECK: nop
0x66 0x90
-# CHECKX: nop
+# CHECK: nop
0x90
# CHECK: xchgl %ecx, %eax
diff --git a/llvm/test/MC/LoongArch/Relocations/relax-align.s b/llvm/test/MC/LoongArch/Relocations/relax-align.s
index 294fd9fb916c7..911f2e8f04aba 100644
--- a/llvm/test/MC/LoongArch/Relocations/relax-align.s
+++ b/llvm/test/MC/LoongArch/Relocations/relax-align.s
@@ -58,7 +58,7 @@ break 6
# RELAX-INSTR-NEXT: nop
ret
-# INSNR-NEXT: ret
+# INSTR-NEXT: ret
## Test the symbol index is different from .text.
.section .text2, "ax"
diff --git a/llvm/test/MC/MachO/lto-set-conditional.s b/llvm/test/MC/MachO/lto-set-conditional.s
index 0007d4a259cbc..1ea26eaa231ec 100644
--- a/llvm/test/MC/MachO/lto-set-conditional.s
+++ b/llvm/test/MC/MachO/lto-set-conditional.s
@@ -57,14 +57,14 @@ a:
# CHECK: Symbol {
# CHECK-NEXT: Name: m
# CHECK: Flags [
-# CHECK-NOT : NoDeadStrip
+# CHECK-NOT: NoDeadStrip
# CHECK: Value: 0x2
m:
# CHECK: Symbol {
# CHECK-NEXT: Name: h
# CHECK: Flags [
-# CHECK-NOT : NoDeadStrip
+# CHECK-NOT: NoDeadStrip
# CHECK: Value: 0x2
.lto_set_conditional h, m
diff --git a/llvm/test/MC/Mips/expansion-jal-sym-pic.s b/llvm/test/MC/Mips/expansion-jal-sym-pic.s
index 1279de10d2503..e843b4a2f4f1b 100644
--- a/llvm/test/MC/Mips/expansion-jal-sym-pic.s
+++ b/llvm/test/MC/Mips/expansion-jal-sym-pic.s
@@ -623,7 +623,7 @@ local_label:
# O32-MM-NEXT: # fixup A - offset: 0, value: %got(.text), kind: fixup_MICROMIPS_GOT16
# O32-MM-NEXT: addiu $25, $25, %lo(.text) # encoding: [0x33,0x39,A,A]
# O32-MM-NEXT: # fixup A - offset: 0, value: %lo(.text), kind: fixup_MICROMIPS_LO16
-# O42-MM-NEXT: .reloc ($tmp3), R_MICROMIPS_JALR, .text
+# O32-MM-NEXT: .reloc ($tmp3), R_MICROMIPS_JALR, .text
# MIPS: jalr $25 # encoding: [0x03,0x20,0xf8,0x09]
# MM: jalr $ra, $25 # encoding: [0x03,0xf9,0x0f,0x3c]
@@ -689,7 +689,7 @@ local_label:
# O32-MM-NEXT: # fixup A - offset: 0, value: %got(.text+8), kind: fixup_MICROMIPS_GOT16
# O32-MM-NEXT: addiu $25, $25, %lo(.text+8) # encoding: [0x33,0x39,A,A]
# O32-MM-NEXT: # fixup A - offset: 0, value: %lo(.text+8), kind: fixup_MICROMIPS_LO16
-# O42-MM-NEXT: .reloc ($tmp4), R_MICROMIPS_JALR, .text
+# O32-MM-NEXT: .reloc ($tmp4), R_MICROMIPS_JALR, .text
# MIPS: jalr $25 # encoding: [0x03,0x20,0xf8,0x09]
# MM: jalr $ra, $25 # encoding: [0x03,0xf9,0x0f,0x3c]
diff --git a/llvm/test/MC/Mips/micromips-dsp/invalid.s b/llvm/test/MC/Mips/micromips-dsp/invalid.s
index 05fc77440d3ef..32fd6406d6b04 100644
--- a/llvm/test/MC/Mips/micromips-dsp/invalid.s
+++ b/llvm/test/MC/Mips/micromips-dsp/invalid.s
@@ -10,15 +10,15 @@
shll.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shll.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
// FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
- shll_s.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
- shll_s.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
+ shll_s.w $3, $4, 32 # COM: CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
+ shll_s.w $3, $4, -1 # COM: CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shra.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shra.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shra_r.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
shra_r.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
// FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
- shra_r.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
- shra_r.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
+ shra_r.w $3, $4, 32 # COM: CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
+ shra_r.w $3, $4, -1 # COM: CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s
index a995c37b15c3a..e3a68cb3bd444 100644
--- a/llvm/test/MC/Mips/micromips/valid.s
+++ b/llvm/test/MC/Mips/micromips/valid.s
@@ -302,13 +302,13 @@ sce $2, 8($4) # CHECK: sce $2, 8($4) # encoding: [0x60,0x
syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c]
syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
# FIXME: ldc1 should accept uneven registers
-# ldc1 $f7, 300($10) # -CHECK: ldc1 $f7, 300($10) # encoding: [0xbc,0xea,0x01,0x2c]
+# ldc1 $f7, 300($10) # COM: CHECK: ldc1 $f7, 300($10) # encoding: [0xbc,0xea,0x01,0x2c]
ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c]
lwc1 $f2, 4($6) # CHECK: lwc1 $f2, 4($6) # encoding: [0x9c,0x46,0x00,0x04]
# CHECK-NEXT: # <MCInst #{{.*}} LWC1_MM
sdc1 $f2, 4($6) # CHECK: sdc1 $f2, 4($6) # encoding: [0xb8,0x46,0x00,0x04]
# FIXME: sdc1 should accept uneven registers
-# sdc1 $f7, 64($10) # -CHECK: sdc1 $f7, 64($10) # encoding: [0xb8,0xea,0x00,0x40]
+# sdc1 $f7, 64($10) # COM: CHECK: sdc1 $f7, 64($10) # encoding: [0xb8,0xea,0x00,0x40]
swc1 $f2, 4($6) # CHECK: swc1 $f2, 4($6) # encoding: [0x98,0x46,0x00,0x04]
# CHECK-NEXT: # <MCInst #{{.*}} SWC1_MM
cfc1 $1, $2 # CHECK: cfc1 $1, $2 # encoding: [0x54,0x22,0x10,0x3b]
diff --git a/llvm/test/MC/Mips/mips-pdr-bad.s b/llvm/test/MC/Mips/mips-pdr-bad.s
index 1e15a8893db2f..5de0b41a47026 100644
--- a/llvm/test/MC/Mips/mips-pdr-bad.s
+++ b/llvm/test/MC/Mips/mips-pdr-bad.s
@@ -5,8 +5,8 @@
.ent # ASM: :[[@LINE]]:14: error: expected identifier after .ent
.ent bar, # ASM: :[[@LINE]]:19: error: expected number after comma
- .ent foo, bar # AMS: :[[@LINE]]:23: error: expected an absolute expression after comma
- .ent foo, 5, bar # AMS: :[[@LINE]]:20: error: unexpected token, expected end of statement
+ .ent foo, bar # ASM: :[[@LINE]]:23: error: expected an absolute expression after comma
+ .ent foo, 5, bar # ASM: :[[@LINE]]:20: error: unexpected token, expected end of statement
.frame # ASM: :[[@LINE]]:16: error: expected stack register
.frame bar # ASM: :[[@LINE]]:16: error: expected stack register
diff --git a/llvm/test/MC/Mips/mips32r6/invalid.s b/llvm/test/MC/Mips/mips32r6/invalid.s
index 7e7b2281957fb..54bac427f86c1 100644
--- a/llvm/test/MC/Mips/mips32r6/invalid.s
+++ b/llvm/test/MC/Mips/mips32r6/invalid.s
@@ -39,14 +39,14 @@ local_label:
lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
// FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved
- bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bltl $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bltul $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ blel $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bleul $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bgel $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bgeul $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bgtl $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bgtul $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgec $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
bltc $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
bgeuc $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
diff --git a/llvm/test/MC/Mips/mips64r6/invalid.s b/llvm/test/MC/Mips/mips64r6/invalid.s
index f9b3707efb106..f1123b0d26f64 100644
--- a/llvm/test/MC/Mips/mips64r6/invalid.s
+++ b/llvm/test/MC/Mips/mips64r6/invalid.s
@@ -65,14 +65,14 @@ local_label:
lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
// FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved
- bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bltl $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bltul $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ blel $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bleul $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bgel $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bgeul $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bgtl $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bgtul $7, $8, local_label # COM: CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
beqc $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
bnec $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
bgec $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
index 03179480147a5..3d51b6fbfd959 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -330,7 +330,7 @@
# CHECK-BE: pstfs 1, 134217727(0), 1 # encoding: [0x06,0x10,0x07,0xff
# CHECK-BE-SAME: 0xd0,0x20,0xff,0xff]
# CHECK-LE: pstfs 1, 134217727(0), 1 # encoding: [0xff,0x07,0x10,0x06,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0xd0]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0xd0]
pstfs 1, 134217727(0), 1
# CHECK-BE: pstfd 1, -134217728(3), 0 # encoding: [0x06,0x03,0xf8,0x00,
# CHECK-BE-SAME: 0xd8,0x23,0x00,0x00]
@@ -340,7 +340,7 @@
# CHECK-BE: pstfd 1, 134217727(0), 1 # encoding: [0x06,0x10,0x07,0xff
# CHECK-BE-SAME: 0xd8,0x20,0xff,0xff]
# CHECK-LE: pstfd 1, 134217727(0), 1 # encoding: [0xff,0x07,0x10,0x06,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0xd8]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0xd8]
pstfd 1, 134217727(0), 1
# CHECK-BE: pstxssp 1, -134217728(3), 0 # encoding: [0x04,0x03,0xf8,0x00,
# CHECK-BE-SAME: 0xbc,0x23,0x00,0x00]
@@ -350,7 +350,7 @@
# CHECK-BE: pstxssp 1, 134217727(0), 1 # encoding: [0x04,0x10,0x07,0xff
# CHECK-BE-SAME: 0xbc,0x20,0xff,0xff]
# CHECK-LE: pstxssp 1, 134217727(0), 1 # encoding: [0xff,0x07,0x10,0x04,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0xbc]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0xbc]
pstxssp 1, 134217727(0), 1
# CHECK-BE: pstxsd 1, -134217728(3), 0 # encoding: [0x04,0x03,0xf8,0x00,
# CHECK-BE-SAME: 0xb8,0x23,0x00,0x00]
@@ -360,7 +360,7 @@
# CHECK-BE: pstxsd 1, 134217727(0), 1 # encoding: [0x04,0x10,0x07,0xff
# CHECK-BE-SAME: 0xb8,0x20,0xff,0xff]
# CHECK-LE: pstxsd 1, 134217727(0), 1 # encoding: [0xff,0x07,0x10,0x04,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0xb8]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0xb8]
pstxsd 1, 134217727(0), 1
# CHECK-BE: plfs 1, -8589934592(3), 0 # encoding: [0x06,0x02,0x00,0x00,
# CHECK-BE-SAME: 0xc0,0x23,0x00,0x00]
@@ -370,7 +370,7 @@
# CHECK-BE: plfs 1, 8589934591(0), 1 # encoding: [0x06,0x11,0xff,0xff
# CHECK-BE-SAME: 0xc0,0x20,0xff,0xff]
# CHECK-LE: plfs 1, 8589934591(0), 1 # encoding: [0xff,0xff,0x11,0x06,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0xc0]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0xc0]
plfs 1, 8589934591(0), 1
# CHECK-BE: plfd 1, -8589934592(3), 0 # encoding: [0x06,0x02,0x00,0x00,
# CHECK-BE-SAME: 0xc8,0x23,0x00,0x00]
@@ -380,7 +380,7 @@
# CHECK-BE: plfd 1, 8589934591(0), 1 # encoding: [0x06,0x11,0xff,0xff
# CHECK-BE-SAME: 0xc8,0x20,0xff,0xff]
# CHECK-LE: plfd 1, 8589934591(0), 1 # encoding: [0xff,0xff,0x11,0x06,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0xc8]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0xc8]
plfd 1, 8589934591(0), 1
# CHECK-BE: plxssp 1, -8589934592(3), 0 # encoding: [0x04,0x02,0x00,0x00,
# CHECK-BE-SAME: 0xac,0x23,0x00,0x00]
@@ -390,7 +390,7 @@
# CHECK-BE: plxssp 1, 8589934591(0), 1 # encoding: [0x04,0x11,0xff,0xff
# CHECK-BE-SAME: 0xac,0x20,0xff,0xff]
# CHECK-LE: plxssp 1, 8589934591(0), 1 # encoding: [0xff,0xff,0x11,0x04,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0xac]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0xac]
plxssp 1, 8589934591(0), 1
# CHECK-BE: plxsd 1, -8589934592(3), 0 # encoding: [0x04,0x02,0x00,0x00,
# CHECK-BE-SAME: 0xa8,0x23,0x00,0x00]
@@ -400,7 +400,7 @@
# CHECK-BE: plxsd 1, 8589934591(0), 1 # encoding: [0x04,0x11,0xff,0xff
# CHECK-BE-SAME: 0xa8,0x20,0xff,0xff]
# CHECK-LE: plxsd 1, 8589934591(0), 1 # encoding: [0xff,0xff,0x11,0x04,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0xa8]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0xa8]
plxsd 1, 8589934591(0), 1
# CHECK-BE: pstb 1, -8589934592(3), 0 # encoding: [0x06,0x02,0x00,0x00,
# CHECK-BE-SAME: 0x98,0x23,0x00,0x00]
@@ -410,7 +410,7 @@
# CHECK-BE: pstb 1, 8589934591(0), 1 # encoding: [0x06,0x11,0xff,0xff
# CHECK-BE-SAME: 0x98,0x20,0xff,0xff]
# CHECK-LE: pstb 1, 8589934591(0), 1 # encoding: [0xff,0xff,0x11,0x06,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0x98]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0x98]
pstb 1, 8589934591(0), 1
# CHECK-BE: psth 1, -8589934592(3), 0 # encoding: [0x06,0x02,0x00,0x00,
# CHECK-BE-SAME: 0xb0,0x23,0x00,0x00]
@@ -420,7 +420,7 @@
# CHECK-BE: psth 1, 8589934591(0), 1 # encoding: [0x06,0x11,0xff,0xff
# CHECK-BE-SAME: 0xb0,0x20,0xff,0xff]
# CHECK-LE: psth 1, 8589934591(0), 1 # encoding: [0xff,0xff,0x11,0x06,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0xb0]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0xb0]
psth 1, 8589934591(0), 1
# CHECK-BE: pstw 1, -8589934592(3), 0 # encoding: [0x06,0x02,0x00,0x00,
# CHECK-BE-SAME: 0x90,0x23,0x00,0x00]
@@ -430,7 +430,7 @@
# CHECK-BE: pstw 1, 8589934591(0), 1 # encoding: [0x06,0x11,0xff,0xff
# CHECK-BE-SAME: 0x90,0x20,0xff,0xff]
# CHECK-LE: pstw 1, 8589934591(0), 1 # encoding: [0xff,0xff,0x11,0x06,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0x90]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0x90]
pstw 1, 8589934591(0), 1
# CHECK-BE: pstd 1, -8589934592(3), 0 # encoding: [0x04,0x02,0x00,0x00,
# CHECK-BE-SAME: 0xf4,0x23,0x00,0x00]
@@ -440,7 +440,7 @@
# CHECK-BE: pstd 1, 8589934591(0), 1 # encoding: [0x04,0x11,0xff,0xff
# CHECK-BE-SAME: 0xf4,0x20,0xff,0xff]
# CHECK-LE: pstd 1, 8589934591(0), 1 # encoding: [0xff,0xff,0x11,0x04,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0xf4]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0xf4]
pstd 1, 8589934591(0), 1
# CHECK-BE: plbz 1, 8589934591(3), 0 # encoding: [0x06,0x01,0xff,0xff
# CHECK-BE-SAME: 0x88,0x23,0xff,0xff]
@@ -490,7 +490,7 @@
# CHECK-BE: plwa 1, 8589934591(0), 1 # encoding: [0x04,0x11,0xff,0xff
# CHECK-BE-SAME: 0xa4,0x20,0xff,0xff]
# CHECK-LE: plwa 1, 8589934591(0), 1 # encoding: [0xff,0xff,0x11,0x04,
-# CECHK-LE-SAME: 0xff,0xff,0x20,0xa4]
+# CHECK-LE-SAME: 0xff,0xff,0x20,0xa4]
plwa 1, 8589934591(0), 1
# CHECK-BE: pld 1, -8589934592(3), 0 # encoding: [0x04,0x02,0x00,0x00,
# CHECK-BE-SAME: 0xe4,0x23,0x00,0x00]
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s b/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
index b2b7b3d9d6a72..4d6e53869eb08 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -738,8 +738,8 @@
# CHECK-LE: vpopcntw 2, 3 # encoding: [0x83,0x1f,0x40,0x10]
vpopcntw 2, 3
-# BCHECK-BE: vpopcntd 2, 3 # encoding: [0x10,0x40,0x1f,0xC3]
-# BCHECK-LE: vpopcntd 2, 3 # encoding: [0xC3,0x1f,0x40,0x10]
+# CHECK-BE: vpopcntd 2, 3 # encoding: [0x10,0x40,0x1f,0xC3]
+# CHECK-LE: vpopcntd 2, 3 # encoding: [0xC3,0x1f,0x40,0x10]
# vpopcntd 2, 3
# Vector status and control register instructions
diff --git a/llvm/test/MC/RISCV/compress-rv64i.s b/llvm/test/MC/RISCV/compress-rv64i.s
index ab5b24307cd1a..a4eba644f60e4 100644
--- a/llvm/test/MC/RISCV/compress-rv64i.s
+++ b/llvm/test/MC/RISCV/compress-rv64i.s
@@ -24,13 +24,13 @@ ld s0, 248(a5)
sd s0, 64(a5)
# CHECK-BYTES: 227d
-# CHEACK-ALIAS: addiw tp, tp, 31
+# CHECK-ALIAS: addiw tp, tp, 31
# CHECK-INST: c.addiw tp, 31
# CHECK: # encoding: [0x7d,0x22]
addiw tp, tp, 31
# CHECK-BYTES: 9c1d
-# CHEACK-ALIAS: subw s0, s0, a5
+# CHECK-ALIAS: subw s0, s0, a5
# CHECK-INST: c.subw s0, a5
# CHECK: # encoding: [0x1d,0x9c]
subw s0, s0, a5
diff --git a/llvm/test/MC/RISCV/csr-aliases.s b/llvm/test/MC/RISCV/csr-aliases.s
index 1d7032fc72a0b..87fce59a86112 100644
--- a/llvm/test/MC/RISCV/csr-aliases.s
+++ b/llvm/test/MC/RISCV/csr-aliases.s
@@ -45,61 +45,61 @@ csrrs t0, 3, zero
# CHECK-INST: csrrw t1, fcsr, t2
# CHECK-ALIAS: fscsr t1, t2
-# CHECK-EXT-F-ON: fscsr t1, t2
+# CHECK-EXT-F: fscsr t1, t2
# CHECK-EXT-F-OFF: csrrw t1, fcsr, t2
csrrw t1, 3, t2
# CHECK-INST: csrrw zero, fcsr, t2
# CHECK-ALIAS: fscsr t2
-# CHECK-EXT-F-ON: fscsr t2
+# CHECK-EXT-F: fscsr t2
# CHECK-EXT-F-OFF: csrw fcsr, t2
csrrw zero, 3, t2
# CHECK-INST: csrrw zero, fcsr, t2
# CHECK-ALIAS: fscsr t2
-# CHECK-EXT-F-ON: fscsr t2
+# CHECK-EXT-F: fscsr t2
# CHECK-EXT-F-OFF: csrw fcsr, t2
csrrw zero, 3, t2
# CHECK-INST: csrrw t0, frm, zero
# CHECK-ALIAS: fsrm t0, zero
-# CHECK-EXT-F-ON: fsrm t0, zero
+# CHECK-EXT-F: fsrm t0, zero
# CHECK-EXT-F-OFF: csrrw t0, frm
csrrw t0, 2, zero
# CHECK-INST: csrrw t0, frm, t1
# CHECK-ALIAS: fsrm t0, t1
-# CHECK-EXT-F-ON: fsrm t0, t1
+# CHECK-EXT-F: fsrm t0, t1
# CHECK-EXT-F-OFF: csrrw t0, frm, t1
csrrw t0, 2, t1
# CHECK-INST: csrrwi t0, frm, 0x1f
# CHECK-ALIAS: fsrmi t0, 0x1f
-# CHECK-EXT-F-ON: fsrmi t0, 0x1f
+# CHECK-EXT-F: fsrmi t0, 0x1f
# CHECK-EXT-F-OFF: csrrwi t0, frm, 0x1f
csrrwi t0, 2, 31
# CHECK-INST: csrrwi zero, frm, 0x1f
# CHECK-ALIAS: fsrmi 0x1f
-# CHECK-EXT-F-ON: fsrmi 0x1f
+# CHECK-EXT-F: fsrmi 0x1f
# CHECK-EXT-F-OFF: csrwi frm, 0x1f
csrrwi zero, 2, 31
# CHECK-INST: csrrs t0, fflags, zero
# CHECK-ALIAS: frflags t0
-# CHECK-EXT-F-ON: frflags t0
+# CHECK-EXT-F: frflags t0
# CHECK-EXT-F-OFF: csrr t0, fflags
csrrs t0, 1, zero
# CHECK-INST: csrrw t0, fflags, t2
# CHECK-ALIAS: fsflags t0, t2
-# CHECK-EXT-F-ON: fsflags t0, t2
+# CHECK-EXT-F: fsflags t0, t2
# CHECK-EXT-F-OFF: csrrw t0, fflags, t2
csrrw t0, 1, t2
# CHECK-INST: csrrw zero, fflags, t2
# CHECK-ALIAS: fsflags t2
-# CHECK-EXT-F-ON: fsflags t2
+# CHECK-EXT-F: fsflags t2
# CHECK-EXT-F-OFF: csrw fflags, t2
csrrw zero, 1, t2
diff --git a/llvm/test/MC/RISCV/relocations.s b/llvm/test/MC/RISCV/relocations.s
index d9d941697704c..e292ba23d01c8 100644
--- a/llvm/test/MC/RISCV/relocations.s
+++ b/llvm/test/MC/RISCV/relocations.s
@@ -180,20 +180,20 @@ bgeu a0, a1, foo
.L5:
auipc a0, %tlsdesc_hi(a_symbol)
# RELOC: R_RISCV_TLSDESC_HI20
-# INST: auipc a0, 0x0
+# INSTR: auipc a0, 0x0
# FIXUP: fixup A - offset: 0, value: %tlsdesc_hi(a_symbol), kind: fixup_riscv_tlsdesc_hi20
lw a1, %tlsdesc_load_lo(.L5)(a0)
# RELOC: R_RISCV_TLSDESC_LOAD_LO12
-# INST: lw a1, 0x0(a0)
+# INSTR: lw a1, 0x0(a0)
# FIXUP: fixup A - offset: 0, value: %tlsdesc_load_lo(.L5), kind: fixup_riscv_tlsdesc_load_lo12
addi a0, a0, %tlsdesc_add_lo(.L5)
# RELOC: R_RISCV_TLSDESC_ADD_LO12
-# INST: addi a0, a0, 0x0
+# INSTR: addi a0, a0, 0x0
# FIXUP: fixup A - offset: 0, value: %tlsdesc_add_lo(.L5), kind: fixup_riscv_tlsdesc_add_lo12
jalr t0, 0(a1), %tlsdesc_call(.L5)
# RELOC: R_RISCV_TLSDESC_CALL
-# INST: jalr t0, 0x0(a1)
+# INSTR: jalr t0, 0x0(a1)
# FIXUP: fixup A - offset: 0, value: %tlsdesc_call(.L5), kind: fixup_riscv_tlsdesc_call
diff --git a/llvm/test/MC/WebAssembly/globals.s b/llvm/test/MC/WebAssembly/globals.s
index b7e25cb9f0519..4df7e0d71c8ee 100644
--- a/llvm/test/MC/WebAssembly/globals.s
+++ b/llvm/test/MC/WebAssembly/globals.s
@@ -33,7 +33,7 @@ global3:
global4:
# CHECK: .globl read_global
-# CNEXT: .globl write_global
+# CHECK: .globl write_global
# CHECK: .globaltype foo_global, i32
# CHECK: foo_global:
diff --git a/llvm/test/MC/X86/apx/evex-format-intel.s b/llvm/test/MC/X86/apx/evex-format-intel.s
index 42d4c0c0081a7..c7cfd1712f7ea 100644
--- a/llvm/test/MC/X86/apx/evex-format-intel.s
+++ b/llvm/test/MC/X86/apx/evex-format-intel.s
@@ -88,8 +88,8 @@
## MRM5m
## AsmParser is buggy for this KNC instruction
-# C;HECK: vscatterpf0dps {k1}, zmmword ptr [r16 + zmm0]
-# C;HECK: encoding: [0x62,0xfa,0x7d,0x49,0xc6,0x2c,0x00]
+# COM: CHECK: vscatterpf0dps {k1}, zmmword ptr [r16 + zmm0]
+# COM: CHECK: encoding: [0x62,0xfa,0x7d,0x49,0xc6,0x2c,0x00]
# vscatterpf0dps {k1}, zmmword ptr [r16 + zmm0]
# CHECK: sub r17, qword ptr [r16 + 123], 127
diff --git a/llvm/test/MC/Xtensa/Relocations/relocations.s b/llvm/test/MC/Xtensa/Relocations/relocations.s
index 19c2e16352509..715e41b77ccd4 100644
--- a/llvm/test/MC/Xtensa/Relocations/relocations.s
+++ b/llvm/test/MC/Xtensa/Relocations/relocations.s
@@ -13,157 +13,157 @@
ball a1, a3, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: ball a1, a3, func
+# INSTR: ball a1, a3, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bany a8, a13, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bany a8, a13, func
+# INSTR: bany a8, a13, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bbc a8, a7, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bbc a8, a7, func
+# INSTR: bbc a8, a7, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bbci a3, 16, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bbci a3, 16, func
+# INSTR: bbci a3, 16, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bbs a12, a5, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bbs a12, a5, func
+# INSTR: bbs a12, a5, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bbsi a3, 16, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bbsi a3, 16, func
+# INSTR: bbsi a3, 16, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bnall a7, a3, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bnall a7, a3, func
+# INSTR: bnall a7, a3, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bnone a2, a4, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bnone a2, a4, func
+# INSTR: bnone a2, a4, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
beq a1, a2, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: beq a1, a2, func
+# INSTR: beq a1, a2, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
beq a11, a5, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: beq a11, a5, func
+# INSTR: beq a11, a5, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
beqi a1, 256, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: beqi a1, 256, func
+# INSTR: beqi a1, 256, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
beqi a11, -1, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: beqi a11, -1, func
+# INSTR: beqi a11, -1, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
beqz a8, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: beqz a8, func
+# INSTR: beqz a8, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_12
bge a14, a2, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bge a14, a2, func
+# INSTR: bge a14, a2, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bgei a11, -1, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bgei a11, -1, func
+# INSTR: bgei a11, -1, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bgei a11, 128, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bgei a11, 128, func
+# INSTR: bgei a11, 128, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bgeu a14, a2, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bgeu a14, a2, func
+# INSTR: bgeu a14, a2, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bgeui a9, 32768, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bgeui a9, 32768, func
+# INSTR: bgeui a9, 32768, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bgeui a7, 65536, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bgeui a7, 65536, func
+# INSTR: bgeui a7, 65536, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bgeui a7, 64, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bgeui a7, 64, func
+# INSTR: bgeui a7, 64, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bgez a8, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bgez a8, func
+# INSTR: bgez a8, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_12
blt a14, a2, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: blt a14, a2, func
+# INSTR: blt a14, a2, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
blti a12, -1, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: blti a12, -1, func
+# INSTR: blti a12, -1, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
blti a0, 32, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: blti a0, 32, func
+# INSTR: blti a0, 32, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bgeu a13, a1, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bgeu a13, a1, func
+# INSTR: bgeu a13, a1, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bltui a7, 16, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bltui a7, 16, func
+# INSTR: bltui a7, 16, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bltz a6, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bltz a6, func
+# INSTR: bltz a6, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_12
bne a3, a4, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bne a3, a4, func
+# INSTR: bne a3, a4, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bnei a5, 12, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bnei a5, 12, func
+# INSTR: bnei a5, 12, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_8
bnez a5, func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: bnez a5, func
+# INSTR: bnez a5, func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_branch_12
call0 func
# RELOC: R_XTENSA_SLOT0_OP
-# INST: call0 func
+# INSTR: call0 func
# FIXUP: fixup A - offset: 0, value: func, kind: fixup_xtensa_call_18
j func
>From c62b2a4939525a6574b64aeedc37b39a24e6ee88 Mon Sep 17 00:00:00 2001
From: klensy <nightouser at gmail.com>
Date: Wed, 29 May 2024 14:26:23 +0300
Subject: [PATCH 3/5] Other
---
.../Other/constant-fold-gep-address-spaces.ll | 94 +++++++++----------
.../Other/new-pm-thinlto-postlink-defaults.ll | 2 +-
2 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/llvm/test/Other/constant-fold-gep-address-spaces.ll b/llvm/test/Other/constant-fold-gep-address-spaces.ll
index e2589ce77ebd2..c0ef2181721ed 100644
--- a/llvm/test/Other/constant-fold-gep-address-spaces.ll
+++ b/llvm/test/Other/constant-fold-gep-address-spaces.ll
@@ -24,31 +24,31 @@ target datalayout = "e-p:128:128:128-p1:32:32:32-p2:8:8:8-p3:16:16:16-p4:64:64:6
; The target-independent folder should be able to do some clever
; simplifications on sizeof, alignof, and offsetof expressions. The
; target-dependent folder should fold these down to constants.
-; PLAIN-X: @a = constant i64 mul (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 2310)
+; PLAIN: @a = constant i64 mul (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 2310)
@a = constant i64 mul (i64 3, i64 mul (i64 ptrtoint (ptr addrspace(4) getelementptr ({[7 x double], [7 x double]}, ptr addrspace(4) null, i64 11) to i64), i64 5))
-; PLAIN-X: @b = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({ i1, double }, ptr null, i64 0, i32 1) to i64)
+; PLAIN: @b = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({ i1, double }, ptr null, i64 0, i32 1) to i64)
@b = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({i1, [13 x double]}, ptr addrspace(4) null, i64 0, i32 1) to i64)
-; PLAIN-X: @c = constant i64 mul nuw (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 2)
+; PLAIN: @c = constant i64 mul nuw (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 2)
@c = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({double, double, double, double}, ptr addrspace(4) null, i64 0, i32 2) to i64)
-; PLAIN-X: @d = constant i64 mul nuw (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 11)
+; PLAIN: @d = constant i64 mul nuw (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 11)
@d = constant i64 ptrtoint (ptr addrspace(4) getelementptr ([13 x double], ptr addrspace(4) null, i64 0, i32 11) to i64)
-; PLAIN-X: @e = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({ double, float, double, double }, ptr null, i64 0, i32 2) to i64)
+; PLAIN: @e = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({ double, float, double, double }, ptr null, i64 0, i32 2) to i64)
@e = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({double, float, double, double}, ptr addrspace(4) null, i64 0, i32 2) to i64)
-; PLAIN-X: @f = constant i64 1
+; PLAIN: @f = constant i64 1
@f = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({i1, <{ i16, i128 }>}, ptr addrspace(4) null, i64 0, i32 1) to i64)
-; PLAIN-X: @g = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({ i1, double }, ptr null, i64 0, i32 1) to i64)
+; PLAIN: @g = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({ i1, double }, ptr null, i64 0, i32 1) to i64)
@g = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({i1, {double, double}}, ptr addrspace(4) null, i64 0, i32 1) to i64)
-; PLAIN-X: @h = constant i64 ptrtoint (ptr addrspace(2) getelementptr (i1, ptr addrspace(2) null, i32 1) to i64)
+; PLAIN: @h = constant i64 ptrtoint (ptr addrspace(2) getelementptr (i1, ptr addrspace(2) null, i32 1) to i64)
@h = constant i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i64 1) to i64)
-; PLAIN-X: @i = constant i64 ptrtoint (ptr addrspace(2) getelementptr ({ i1, ptr addrspace(2) }, ptr null, i64 0, i32 1) to i64)
+; PLAIN: @i = constant i64 ptrtoint (ptr addrspace(2) getelementptr ({ i1, ptr addrspace(2) }, ptr null, i64 0, i32 1) to i64)
@i = constant i64 ptrtoint (ptr addrspace(4) getelementptr ({i1, double}, ptr addrspace(4) null, i64 0, i32 1) to i64)
; The target-dependent folder should cast GEP indices to integer-sized pointers.
@@ -63,11 +63,11 @@ target datalayout = "e-p:128:128:128-p1:32:32:32-p2:8:8:8-p3:16:16:16-p4:64:64:6
; Fold GEP of a GEP. Very simple cases are folded.
-; PLAIN-X: @Y = global ptraddrspace(3) getelementptr inbounds ([3 x { i32, i32 }], ptraddrspace(3) @ext, i64 2)
+; PLAIN: @Y = global ptraddrspace(3) getelementptr inbounds ([3 x { i32, i32 }], ptraddrspace(3) @ext, i64 2)
@ext = external addrspace(3) global [3 x { i32, i32 }]
@Y = global ptr addrspace(3) getelementptr inbounds ([3 x { i32, i32 }], ptr addrspace(3) getelementptr inbounds ([3 x { i32, i32 }], ptr addrspace(3) @ext, i64 1), i64 1)
-; PLAIN-X: @Z = global ptraddrspace(3) getelementptr inbounds (i32, ptr addrspace(3) getelementptr inbounds ([3 x { i32, i32 }], ptr addrspace(3) @ext, i64 0, i64 1, i32 0), i64 1)
+; PLAIN: @Z = global ptraddrspace(3) getelementptr inbounds (i32, ptr addrspace(3) getelementptr inbounds ([3 x { i32, i32 }], ptr addrspace(3) @ext, i64 0, i64 1, i32 0), i64 1)
@Z = global ptr addrspace(3) getelementptr inbounds (i32, ptr addrspace(3) getelementptr inbounds ([3 x { i32, i32 }], ptr addrspace(3) @ext, i64 0, i64 1, i32 0), i64 1)
@@ -123,42 +123,42 @@ define ptr addrspace(2) @hoo1() #0 {
ret ptr addrspace(2) %t
}
-; PLAIN-X: define i64 @fa() #0 {
-; PLAIN-X: %t = bitcast i64 mul (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 2310) to i64
-; PLAIN-X: ret i64 %t
-; PLAIN-X: }
-; PLAIN-X: define i64 @fb() #0 {
-; PLAIN-X: %t = bitcast i64 ptrtoint (ptr addrspace(4) getelementptr ({ i1, double }, ptr null, i64 0, i32 1) to i64) to i64
-; PLAIN-X: ret i64 %t
-; PLAIN-X: }
-; PLAIN-X: define i64 @fc() #0 {
-; PLAIN-X: %t = bitcast i64 mul nuw (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 2) to i64
-; PLAIN-X: ret i64 %t
-; PLAIN-X: }
-; PLAIN-X: define i64 @fd() #0 {
-; PLAIN-X: %t = bitcast i64 mul nuw (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 11) to i64
-; PLAIN-X: ret i64 %t
-; PLAIN-X: }
-; PLAIN-X: define i64 @fe() #0 {
-; PLAIN-X: %t = bitcast i64 ptrtoint (ptr addrspace(4) getelementptr ({ double, float, double, double }, ptr null, i64 0, i32 2) to i64) to i64
-; PLAIN-X: ret i64 %t
-; PLAIN-X: }
-; PLAIN-X: define i64 @ff() #0 {
-; PLAIN-X: %t = bitcast i64 1 to i64
-; PLAIN-X: ret i64 %t
-; PLAIN-X: }
-; PLAIN-X: define i64 @fg() #0 {
-; PLAIN-X: %t = bitcast i64 ptrtoint (ptr addrspace(4) getelementptr ({ i1, double }, ptr null, i64 0, i32 1) to i64) to i64
-; PLAIN-X: ret i64 %t
-; PLAIN-X: }
-; PLAIN-X: define i64 @fh() #0 {
-; PLAIN-X: %t = bitcast i64 ptrtoint (ptr addrspace(2) getelementptr (i1, ptr addrspace(2) null, i32 1) to i64) to i64
-; PLAIN-X: ret i64 %t
-; PLAIN-X: }
-; PLAIN-X: define i64 @fi() #0 {
-; PLAIN-X: %t = bitcast i64 ptrtoint (ptr addrspace(2) getelementptr ({ i1, ptr addrspace(2) }, ptr null, i64 0, i32 1) to i64) to i64
-; PLAIN-X: ret i64 %t
-; PLAIN-X: }
+; PLAIN: define i64 @fa() #0 {
+; PLAIN: %t = bitcast i64 mul (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 2310) to i64
+; PLAIN: ret i64 %t
+; PLAIN: }
+; PLAIN: define i64 @fb() #0 {
+; PLAIN: %t = bitcast i64 ptrtoint (ptr addrspace(4) getelementptr ({ i1, double }, ptr null, i64 0, i32 1) to i64) to i64
+; PLAIN: ret i64 %t
+; PLAIN: }
+; PLAIN: define i64 @fc() #0 {
+; PLAIN: %t = bitcast i64 mul nuw (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 2) to i64
+; PLAIN: ret i64 %t
+; PLAIN: }
+; PLAIN: define i64 @fd() #0 {
+; PLAIN: %t = bitcast i64 mul nuw (i64 ptrtoint (ptr addrspace(4) getelementptr (double, ptr addrspace(4) null, i32 1) to i64), i64 11) to i64
+; PLAIN: ret i64 %t
+; PLAIN: }
+; PLAIN: define i64 @fe() #0 {
+; PLAIN: %t = bitcast i64 ptrtoint (ptr addrspace(4) getelementptr ({ double, float, double, double }, ptr null, i64 0, i32 2) to i64) to i64
+; PLAIN: ret i64 %t
+; PLAIN: }
+; PLAIN: define i64 @ff() #0 {
+; PLAIN: %t = bitcast i64 1 to i64
+; PLAIN: ret i64 %t
+; PLAIN: }
+; PLAIN: define i64 @fg() #0 {
+; PLAIN: %t = bitcast i64 ptrtoint (ptr addrspace(4) getelementptr ({ i1, double }, ptr null, i64 0, i32 1) to i64) to i64
+; PLAIN: ret i64 %t
+; PLAIN: }
+; PLAIN: define i64 @fh() #0 {
+; PLAIN: %t = bitcast i64 ptrtoint (ptr addrspace(2) getelementptr (i1, ptr addrspace(2) null, i32 1) to i64) to i64
+; PLAIN: ret i64 %t
+; PLAIN: }
+; PLAIN: define i64 @fi() #0 {
+; PLAIN: %t = bitcast i64 ptrtoint (ptr addrspace(2) getelementptr ({ i1, ptr addrspace(2) }, ptr null, i64 0, i32 1) to i64) to i64
+; PLAIN: ret i64 %t
+; PLAIN: }
define i64 @fa() #0 {
%t = bitcast i64 mul (i64 3, i64 mul (i64 ptrtoint (ptr getelementptr ({[7 x double], [7 x double]}, ptr null, i64 11) to i64), i64 5)) to i64
ret i64 %t
diff --git a/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
index 064362eabbf83..03c9d3623fee7 100644
--- a/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
+++ b/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
@@ -62,7 +62,7 @@
; CHECK-O-NEXT: Running analysis: OuterAnalysisManagerProxy
; CHECK-O-NEXT: Running pass: SimplifyCFGPass
; CHECK-O-NEXT: Running pass: AlwaysInlinerPass
-; CHECK-PRELINK-O-NEXT: Running analysis: ProfileSummaryAnalysis
+; CHECK-POSTLINK-O-NEXT: Running analysis: ProfileSummaryAnalysis
; CHECK-O-NEXT: Running pass: ModuleInlinerWrapperPass
; CHECK-O-NEXT: Running analysis: InlineAdvisorAnalysis
; CHECK-O-NEXT: Running pass: RequireAnalysisPass<{{.*}}GlobalsAA
>From 3e6f58b17fba9cbbc457a5081a3d5e417657ef90 Mon Sep 17 00:00:00 2001
From: klensy <nightouser at gmail.com>
Date: Wed, 29 May 2024 14:06:45 +0300
Subject: [PATCH 4/5] tools
---
llvm/test/tools/gold/X86/global_with_section.ll | 2 +-
llvm/test/tools/llvm-cov/coverage_watermark.test | 10 +++++-----
llvm/test/tools/llvm-cov/zeroFunctionFile.c | 2 +-
llvm/test/tools/llvm-objcopy/ELF/update-section.test | 2 +-
.../tools/llvm-objdump/X86/start-stop-address.test | 2 +-
.../tools/llvm-profgen/filter-ambiguous-profile.test | 10 +++++-----
.../tools/llvm-reduce/mir/reduce-register-defs.mir | 2 +-
llvm/test/tools/llvm-reduce/skip-delta-passes.ll | 2 +-
llvm/test/tools/lto/discard-value-names.ll | 2 +-
9 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/llvm/test/tools/gold/X86/global_with_section.ll b/llvm/test/tools/gold/X86/global_with_section.ll
index 2ba0a16e23782..e4ec41ea4dc59 100644
--- a/llvm/test/tools/gold/X86/global_with_section.ll
+++ b/llvm/test/tools/gold/X86/global_with_section.ll
@@ -45,7 +45,7 @@ target triple = "x86_64-unknown-linux-gnu"
; Confirm via a variable with a non-C identifier section that we are getting
; the expected internalization.
-; CHECK-REGULARLTO-DAG: @var_with_nonC_section = internal global i32 0, section ".nonCsection"
+; CHECK2-REGULARLTO-DAG: @var_with_nonC_section = internal global i32 0, section ".nonCsection"
; Check we dropped definition of dead variable.
; CHECK-THINLTO-NOT: @var_with_nonC_section
@var_with_nonC_section = global i32 0, section ".nonCsection"
diff --git a/llvm/test/tools/llvm-cov/coverage_watermark.test b/llvm/test/tools/llvm-cov/coverage_watermark.test
index 5c48b4f0fb4bf..97b9d240e0b09 100644
--- a/llvm/test/tools/llvm-cov/coverage_watermark.test
+++ b/llvm/test/tools/llvm-cov/coverage_watermark.test
@@ -29,7 +29,7 @@ ORIGIN: </tr>
RUN: llvm-cov show %S/Inputs/templateInstantiations.covmapping -instr-profile %S/Inputs/templateInstantiations.profdata -format html -show-region-summary -show-instantiation-summary -o %t.html.dir -path-equivalence=/tmp,%S -coverage-watermark 80,70 %S/showTemplateInstantiations.cpp
RUN: FileCheck -check-prefix=DOWNGRADE1 %s -input-file %t.html.dir/index.html
-DOWNGRADE:1 Totals
+DOWNGRADE1: Totals
DOWNGRADE1: <td class='column-entry-green'>
DOWNGRADE1: 100.00% (2/2)
DOWNGRADE1: <td class='column-entry-green'>
@@ -45,7 +45,7 @@ DOWNGRADE1: </tr>
RUN: llvm-cov show %S/Inputs/templateInstantiations.covmapping -instr-profile %S/Inputs/templateInstantiations.profdata -format html -show-region-summary -show-instantiation-summary -o %t.html.dir -path-equivalence=/tmp,%S -coverage-watermark 70,50 %S/showTemplateInstantiations.cpp
RUN: FileCheck -check-prefix=DOWNGRADE2 %s -input-file %t.html.dir/index.html
-DOWNGRADE:1 Totals
+DOWNGRADE2: Totals
DOWNGRADE2: <td class='column-entry-green'>
DOWNGRADE2: 100.00% (2/2)
DOWNGRADE2: <td class='column-entry-green'>
@@ -54,6 +54,6 @@ DOWNGRADE2: <td class='column-entry-green'>
DOWNGRADE2: 75.00% (9/12)
DOWNGRADE2: <td class='column-entry-yellow'>
DOWNGRADE2: 66.67% (4/6)
-DOWNGRADE1: <td class='column-entry-gray'>
-DOWNGRADE1: - (0/0)
-DOWNGRADE1: </tr>
+DOWNGRADE2: <td class='column-entry-gray'>
+DOWNGRADE2: - (0/0)
+DOWNGRADE2: </tr>
diff --git a/llvm/test/tools/llvm-cov/zeroFunctionFile.c b/llvm/test/tools/llvm-cov/zeroFunctionFile.c
index f463007fe7f60..1e5467d497aaa 100644
--- a/llvm/test/tools/llvm-cov/zeroFunctionFile.c
+++ b/llvm/test/tools/llvm-cov/zeroFunctionFile.c
@@ -15,6 +15,6 @@ int main() {
// RUN: llvm-cov show -j 1 %S/Inputs/zeroFunctionFile.covmapping -format html -instr-profile %t.profdata -o %t.dir
// RUN: FileCheck %s -input-file=%t.dir/index.html -check-prefix=HTML
-// HTML-NO: 0.00% (0/0)
+// HTML-NOT: 0.00% (0/0)
// HTML: Files which contain no functions
// HTML: zeroFunctionFile.h
diff --git a/llvm/test/tools/llvm-objcopy/ELF/update-section.test b/llvm/test/tools/llvm-objcopy/ELF/update-section.test
index 79cfe0e719418..49a533e2221dd 100644
--- a/llvm/test/tools/llvm-objcopy/ELF/update-section.test
+++ b/llvm/test/tools/llvm-objcopy/ELF/update-section.test
@@ -160,7 +160,7 @@ ProgramHeaders:
# LONG-SAME: {{ }}9{{$}}
# LONG: SectionData (
# LONG-NEXT: |111122223|
-# LONT-NEXT: )
+# LONG-NEXT: )
# ADD-UPDATE: Name: .added
# ADD-UPDATE: Size:
diff --git a/llvm/test/tools/llvm-objdump/X86/start-stop-address.test b/llvm/test/tools/llvm-objdump/X86/start-stop-address.test
index c2d51e4b1fdf7..7e38bbb22ef1f 100644
--- a/llvm/test/tools/llvm-objdump/X86/start-stop-address.test
+++ b/llvm/test/tools/llvm-objdump/X86/start-stop-address.test
@@ -16,7 +16,7 @@
// CHECK-NEXT: 2b: 48 8b 45 f0 movq -16(%rbp), %rax
// CHECK-NOT: {{.}}
-// CROSSECTION-NOT: Disassembly
+// CROSSSECTION-NOT: Disassembly
// CROSSSECTION: Disassembly of section .text:
// CROSSSECTION-EMPTY:
// CROSSSECTION-NEXT: <foo>:
diff --git a/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test b/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test
index 3a264e3b1108b..cb067d53d74af 100644
--- a/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test
+++ b/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test
@@ -1,8 +1,8 @@
; RUN: llvm-profgen --format=text --llvm-sample-profile=%S/Inputs/filter-ambiguous-profile.prof --binary=%S/Inputs/inline-cs-noprobe.perfbin --csspgo-preinliner=0 --output=%t1 || FileCheck %s --input-file %t1
;CHECK: foo:12345:1000
-;CHECK-NEXT 1: 1000
-;CHECK-NEXT 4: bar:1000
-;CHECK-NEXT 1: 1000
-;CHECK-NEXT 3: goo:300
-;CHECK-NEXT 1: 300
+;CHECK-NEXT: 1: 1000
+;CHECK-NEXT: 4: bar:1000
+;CHECK-NEXT: 1: 1000
+;CHECK-NEXT: 3: goo:300
+;CHECK-NEXT: 1: 300
diff --git a/llvm/test/tools/llvm-reduce/mir/reduce-register-defs.mir b/llvm/test/tools/llvm-reduce/mir/reduce-register-defs.mir
index 6fb9d5f3e5243..93648d4c428d8 100644
--- a/llvm/test/tools/llvm-reduce/mir/reduce-register-defs.mir
+++ b/llvm/test/tools/llvm-reduce/mir/reduce-register-defs.mir
@@ -170,7 +170,7 @@ body: |
# RESULT0: %exec_copy0:sreg_64_xexec = S_MOV_B64_term $exec
# RESULT0-NEXT: %exec_copy1:sreg_64_xexec = S_MOV_B64_term $exec
-# RESULT-NEXT: S_CBRANCH_EXECZ
+# RESULT0-NEXT: S_CBRANCH_EXECZ
---
name: terminator_def
tracksRegLiveness: true
diff --git a/llvm/test/tools/llvm-reduce/skip-delta-passes.ll b/llvm/test/tools/llvm-reduce/skip-delta-passes.ll
index b1f9cfc9a2bfa..d18982d3f8352 100644
--- a/llvm/test/tools/llvm-reduce/skip-delta-passes.ll
+++ b/llvm/test/tools/llvm-reduce/skip-delta-passes.ll
@@ -11,7 +11,7 @@
; RESULT: define void @foo() {
; RESULT-NEXT: store i32
; RESULT-NEXT: ret void
-; RESULT0-NOT: attributes
+; RESULT-NOT: attributes
; ERROR: unknown pass "foo"
define void @foo() #0 {
diff --git a/llvm/test/tools/lto/discard-value-names.ll b/llvm/test/tools/lto/discard-value-names.ll
index 04d25eaf6067c..2c236f5266cd8 100644
--- a/llvm/test/tools/lto/discard-value-names.ll
+++ b/llvm/test/tools/lto/discard-value-names.ll
@@ -14,7 +14,7 @@
; DISCARD: %add = add i32
; KEEP: %cmp.i = icmp
-; KEEP : %add = add i32
+; KEEP: %add = add i32
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.10.0"
>From 3336bb30b67f8145f9f599d66c57fbac64007911 Mon Sep 17 00:00:00 2001
From: klensy <nightouser at gmail.com>
Date: Wed, 29 May 2024 14:04:51 +0300
Subject: [PATCH 5/5] Transforms
---
.../Transforms/Attributor/cb_liveness_disabled.ll | 4 ++--
.../Transforms/Attributor/cb_liveness_enabled.ll | 4 ++--
llvm/test/Transforms/Attributor/returned.ll | 2 +-
.../Transforms/CallSiteSplitting/callsite-split.ll | 2 +-
llvm/test/Transforms/FunctionAttrs/nonnull.ll | 2 +-
llvm/test/Transforms/GVNSink/sink-common-code.ll | 12 ++++++------
.../Transforms/LoopVectorize/AArch64/strict-fadd.ll | 2 +-
llvm/test/Transforms/LoopVectorize/branch-weights.ll | 4 ++--
llvm/test/Transforms/ObjCARC/rv.ll | 6 +++---
.../PGOProfile/counter_promo_exit_catchswitch.ll | 2 +-
.../PGOProfile/icp_covariant_invoke_return.ll | 8 ++++----
.../Transforms/SimplifyCFG/branch-fold-threshold.ll | 4 ++--
12 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/llvm/test/Transforms/Attributor/cb_liveness_disabled.ll b/llvm/test/Transforms/Attributor/cb_liveness_disabled.ll
index 1f73eea5870de..9ef980e3cd9b5 100644
--- a/llvm/test/Transforms/Attributor/cb_liveness_disabled.ll
+++ b/llvm/test/Transforms/Attributor/cb_liveness_disabled.ll
@@ -189,8 +189,8 @@ define i32 @test_ncheck2(i32 %0) #0 {
attributes #0 = { noinline nounwind sspstrong uwtable}
-; TUNIT_: !0 = !{i32 0, i32 101}
-; TUNIT_: !1 = !{i32 100, i32 201}
+; TUNIT: !0 = !{i32 0, i32 101}
+; TUNIT: !1 = !{i32 100, i32 201}
;.
; TUNIT: attributes #[[ATTR0]] = { mustprogress nofree noinline norecurse nosync nounwind sspstrong willreturn memory(none) uwtable }
; TUNIT: attributes #[[ATTR1:[0-9]+]] = { nofree nosync nounwind willreturn memory(none) }
diff --git a/llvm/test/Transforms/Attributor/cb_liveness_enabled.ll b/llvm/test/Transforms/Attributor/cb_liveness_enabled.ll
index 88fe6ddd37461..663a4359ba00e 100644
--- a/llvm/test/Transforms/Attributor/cb_liveness_enabled.ll
+++ b/llvm/test/Transforms/Attributor/cb_liveness_enabled.ll
@@ -192,8 +192,8 @@ define i32 @test_ncheck2(i32 %0) #0 {
attributes #0 = { noinline nounwind sspstrong uwtable}
-; TUNIT_: !0 = !{i32 0, i32 101}
-; TUNIT_: !1 = !{i32 100, i32 201}
+; TUNIT: !0 = !{i32 0, i32 101}
+; TUNIT: !1 = !{i32 100, i32 201}
;.
; TUNIT: attributes #[[ATTR0]] = { mustprogress nofree noinline norecurse nosync nounwind sspstrong willreturn memory(none) uwtable }
; TUNIT: attributes #[[ATTR1:[0-9]+]] = { nofree nosync nounwind willreturn memory(none) }
diff --git a/llvm/test/Transforms/Attributor/returned.ll b/llvm/test/Transforms/Attributor/returned.ll
index e94cb95069694..2908bfff1bdde 100644
--- a/llvm/test/Transforms/Attributor/returned.ll
+++ b/llvm/test/Transforms/Attributor/returned.ll
@@ -1415,7 +1415,7 @@ define ptr @dont_use_const() #0 {
;
; Verify we do not derive constraints for @_Z3fooP1X as if it was returning `null`.
;
-; CHEKC-NOT: noalias
+; CHECK-NOT: noalias
; CHECK-NOT: align 536870912
%struct.Y = type { %struct.X }
diff --git a/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll b/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll
index 256261d0dd11f..ea8abfb554d12 100644
--- a/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll
+++ b/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll
@@ -72,7 +72,7 @@ declare void @dummy1(ptr, ptr, ptr, ptr, ptr, ptr)
;CHECK: call void @dummy4()
;CHECK-LABEL: NextCond.split:
;CHECK: call void @dummy3()
-;CheCK-LABEL: CallSiteBB:
+;CHECK-LABEL: CallSiteBB:
;CHECK: call void @foo(i1 %tobool1)
define void @caller2(i1 %c, ptr %a_elt, ptr %b_elt, ptr %c_elt) {
entry:
diff --git a/llvm/test/Transforms/FunctionAttrs/nonnull.ll b/llvm/test/Transforms/FunctionAttrs/nonnull.ll
index 4432c4f3c541a..985f570b6300e 100644
--- a/llvm/test/Transforms/FunctionAttrs/nonnull.ll
+++ b/llvm/test/Transforms/FunctionAttrs/nonnull.ll
@@ -716,7 +716,7 @@ declare i8 @use1safecall(ptr %x) nounwind willreturn ; nounwind+willreturn guara
; Without noundef, nonnull cannot be propagated to the parent
define void @parent_poison(ptr %a) {
-; FNATTR-LABEL: @parent_poison(ptr %a)
+; FNATTRS-LABEL: @parent_poison(ptr %a)
; FNATTRS-LABEL: define void @parent_poison(
; FNATTRS-SAME: ptr [[A:%.*]]) {
; FNATTRS-NEXT: call void @use1nonnull_without_noundef(ptr [[A]])
diff --git a/llvm/test/Transforms/GVNSink/sink-common-code.ll b/llvm/test/Transforms/GVNSink/sink-common-code.ll
index 5c83a19c35cf1..c5871bb8e8404 100644
--- a/llvm/test/Transforms/GVNSink/sink-common-code.ll
+++ b/llvm/test/Transforms/GVNSink/sink-common-code.ll
@@ -78,12 +78,12 @@ declare i32 @foo(i32, i32) nounwind readnone
; ret i32 %ret
;}
;
-; -CHECK-LABEL: test3
-; -CHECK: select
-; -CHECK: call
-; -CHECK: call
-; -CHECK: add
-; -CHECK-NOT: br
+; COM: CHECK-LABEL: test3
+; COM: CHECK: select
+; COM: CHECK: call
+; COM: CHECK: call
+; COM: CHECK: add
+; COM: CHECK-NOT: br
define i32 @test4(i1 zeroext %flag, i32 %x, ptr %y) {
entry:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
index 7c1247e9ebc8f..36a8b366381ba 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
@@ -911,7 +911,7 @@ define float @fadd_scalar_vf_fmf(ptr noalias nocapture readonly %a, i64 %n) {
; CHECK-UNORDERED: [[SUM_07:%.*]] = phi float [ [[MERGE_RDX]], %scalar.ph ], [ [[FADD5:%.*]], %for.body ]
; CHECK-UNORDERED: [[LOAD5:%.*]] = load float, ptr
; CHECK-UNORDERED: [[FADD5]] = fadd nnan float [[LOAD5]], [[SUM_07]]
-; CHECK-UORDERED: for.end
+; CHECK-UNORDERED: for.end
; CHECK-UNORDERED: [[RES:%.*]] = phi float [ [[FADD5]], %for.body ], [ [[BIN_RDX3]], %middle.block ]
; CHECK-UNORDERED: ret float [[RES]]
diff --git a/llvm/test/Transforms/LoopVectorize/branch-weights.ll b/llvm/test/Transforms/LoopVectorize/branch-weights.ll
index e4baae43aa797..56b2f70dacbe4 100644
--- a/llvm/test/Transforms/LoopVectorize/branch-weights.ll
+++ b/llvm/test/Transforms/LoopVectorize/branch-weights.ll
@@ -75,8 +75,8 @@ exit:
; CHECK: [[PROF_F0_ENTRY]] = !{!"branch_weights", i32 12, i32 1}
; CHECK: [[PROF_F0_UNLIKELY]] = !{!"branch_weights", i32 1, i32 127}
-; CEHCK: [[PROF_F0_VECTOR_BODY]] = !{!"branch_weights", i32 1, i32 307}
+; CHECK: [[PROF_F0_VECTOR_BODY]] = !{!"branch_weights", i32 1, i32 307}
; CHECK: [[PROF_F0_MIDDLE_BLOCKS]] = !{!"branch_weights", i32 1, i32 3}
; CHECK: [[PROF_F0_VEC_EPILOGUE_SKIP]] = !{!"branch_weights", i32 4, i32 0}
; CHECK: [[PROF_F0_VEC_EPILOG_VECTOR_BODY]] = !{!"branch_weights", i32 0, i32 0}
-; CEHCK: [[PROF_F0_LOOP]] = !{!"branch_weights", i32 2, i32 1}
+; CHECK: [[PROF_F0_LOOP]] = !{!"branch_weights", i32 2, i32 1}
diff --git a/llvm/test/Transforms/ObjCARC/rv.ll b/llvm/test/Transforms/ObjCARC/rv.ll
index ae35d28e5b011..209b49b30f4a5 100644
--- a/llvm/test/Transforms/ObjCARC/rv.ll
+++ b/llvm/test/Transforms/ObjCARC/rv.ll
@@ -103,9 +103,9 @@ entry:
; directly to a return value.
; TODO
-; HECK: define ptr @test5
-; HECK: call ptr @returner()
-; HECK-NEXT: ret ptr %call
+; COM: CHECK: define ptr @test5
+; COM: CHECK: call ptr @returner()
+; COM: CHECK-NEXT: ret ptr %call
;define ptr @test5() {
;entry:
; %call = call ptr @returner()
diff --git a/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll b/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll
index d279f342666a7..f30abc32468e7 100644
--- a/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll
+++ b/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll
@@ -37,7 +37,7 @@ for.cond: ; preds = %for.inc, %entry
for.body: ; preds = %for.cond
; CHECK: for.body:
; NOTENTRY: %pgocount1 = load i64, ptr @"__profc_?run@@YAXH at Z"
-; TENTRY: %pgocount1 = load i64, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH at Z", i32 0, i32 1)
+; ENTRY: %pgocount1 = load i64, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH at Z", i32 0, i32 1)
; CHECK: %1 = add i64 %pgocount1, 1
; NOTENTRY: store i64 %1, ptr @"__profc_?run@@YAXH at Z"
; ENTRY: store i64 %1, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH at Z", i32 0, i32 1)
diff --git a/llvm/test/Transforms/PGOProfile/icp_covariant_invoke_return.ll b/llvm/test/Transforms/PGOProfile/icp_covariant_invoke_return.ll
index 5e23c93af71d0..9deffd715f448 100644
--- a/llvm/test/Transforms/PGOProfile/icp_covariant_invoke_return.ll
+++ b/llvm/test/Transforms/PGOProfile/icp_covariant_invoke_return.ll
@@ -35,16 +35,16 @@ invoke.cont:
; ICALL-PROM: [[DIRCALL_RET:%[0-9]+]] = invoke ptr @_ZN1D4funcEv(ptr %call)
; ICALL-PROM-NEXT: to label %if.end.icp unwind label %lpad
; ICALL-PROM:if.false.orig_indirect:
-; ICAll-PROM: %call2 = invoke ptr %tmp3(ptr %call)
-; ICAll-PROM: to label %invoke.cont1 unwind label %lpad
+; ICALL-PROM: %call2 = invoke ptr %tmp3(ptr %call)
+; ICALL-PROM: to label %invoke.cont1 unwind label %lpad
; ICALL-PROM:if.end.icp:
; ICALL-PROM: br label %invoke.cont1
%call2 = invoke ptr %tmp3(ptr %call)
to label %invoke.cont1 unwind label %lpad, !prof !1
invoke.cont1:
-; ICAll-PROM: [[PHI_RET:%[0-9]+]] = phi ptr [ %call2, %if.false.orig_indirect ], [ [[DIRCALL_RET]], %if.end.icp ]
-; ICAll-PROM: %isnull = icmp eq ptr [[PHI_RET]], null
+; ICALL-PROM: [[PHI_RET:%[0-9]+]] = phi ptr [ %call2, %if.false.orig_indirect ], [ [[DIRCALL_RET]], %if.end.icp ]
+; ICALL-PROM: %isnull = icmp eq ptr [[PHI_RET]], null
%isnull = icmp eq ptr %call2, null
br i1 %isnull, label %delete.end, label %delete.notnull
diff --git a/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll b/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
index 5012b428bc8a8..c6bf89c575a34 100644
--- a/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
+++ b/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
@@ -67,8 +67,8 @@ lor.lhs.false:
%cmp1 = icmp slt i32 %add, %b
br i1 %cmp1, label %cond.false, label %cond.end
; NORMAL-LABEL: lor.lhs.false:
-; AGGRESIVE-LABEL: lor.lhs.false:
-; WAYAGGRESIVE-LABEL: lor.lhs.false:
+; AGGRESSIVE-LABEL: lor.lhs.false:
+; WAYAGGRESSIVE-LABEL: lor.lhs.false:
; NORMAL: br i1
; AGGRESSIVE: br i1
; WAYAGGRESSIVE-NOT: br i1
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