[llvm] [AMDGPU] Reserved private memory register during PEI (PR #93536)

[via llvm-commits]

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@@ -2083,6 +2083,9 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
 
   assert(SPAdj == 0 && "unhandled SP adjustment in call sequence?");
 
+  MachineRegisterInfo &MRI = MF->getRegInfo();
+  assert(MRI.isReserved(MFI->getScratchRSrcReg()));
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PankajDwivedi-25 wrote:

sure arsenm, Thank you for the review.

https://github.com/llvm/llvm-project/pull/93536