[llvm] [AMDGPU][test] Fix the wrong os names in triple. NFC (PR #93501)
Lu Weining via llvm-commits
llvm-commits at lists.llvm.org
Tue May 28 17:32:17 PDT 2024
https://github.com/SixWeining updated https://github.com/llvm/llvm-project/pull/93501
>From 094810997f8c5febe886e4daf4f24815bccce363 Mon Sep 17 00:00:00 2001
From: Weining Lu <luweining at loongson.cn>
Date: Tue, 28 May 2024 11:43:55 +0800
Subject: [PATCH 1/3] [AMDGPU][test] Fix the wrong os names in triple. NFC
hsa -> amdhsa
---
.../CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll | 8 ++++----
.../CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
index 9547f08d3eba6..6b0a0ea5a2cfc 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
-; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-GISEL %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-SDAG %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
index 14fe4e5f48c67..f9408cfd05267 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH-SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH-GISEL %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH-SDAG %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
>From d0d68e68571f0abd5cc8e56480ca34316927bee7 Mon Sep 17 00:00:00 2001
From: Weining Lu <luweining at loongson.cn>
Date: Tue, 28 May 2024 20:49:55 +0800
Subject: [PATCH 2/3] remove incorrect tests
---
.../lower-work-group-id-intrinsics-hsa.ll | 122 +++++++----------
.../lower-work-group-id-intrinsics-pal.ll | 126 ------------------
2 files changed, 47 insertions(+), 201 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
index 6b0a0ea5a2cfc..22c6a24e9272d 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
@@ -3,15 +3,13 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-GISEL %s
-; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
define amdgpu_kernel void @workgroup_ids_kernel() {
; GFX9-LABEL: workgroup_ids_kernel:
; GFX9: ; %bb.0: ; %.entry
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
; GFX9-NEXT: s_endpgm
;
@@ -72,27 +70,20 @@ define amdgpu_kernel void @workgroup_ids_kernel() {
define amdgpu_kernel void @caller() {
; GFX9-SDAG-LABEL: caller:
; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; GFX9-SDAG-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; GFX9-SDAG-NEXT: s_mov_b32 s38, -1
-; GFX9-SDAG-NEXT: s_mov_b32 s39, 0xe00000
-; GFX9-SDAG-NEXT: s_add_u32 s36, s36, s7
-; GFX9-SDAG-NEXT: s_addc_u32 s37, s37, 0
-; GFX9-SDAG-NEXT: s_add_u32 s8, s2, 36
-; GFX9-SDAG-NEXT: s_addc_u32 s9, s3, 0
-; GFX9-SDAG-NEXT: s_getpc_b64 s[2:3]
-; GFX9-SDAG-NEXT: s_add_u32 s2, s2, callee at gotpcrel32@lo+4
-; GFX9-SDAG-NEXT: s_addc_u32 s3, s3, callee at gotpcrel32@hi+12
-; GFX9-SDAG-NEXT: s_load_dwordx2 s[14:15], s[2:3], 0x0
-; GFX9-SDAG-NEXT: s_mov_b64 s[10:11], s[4:5]
+; GFX9-SDAG-NEXT: s_add_u32 flat_scratch_lo, s10, s13
+; GFX9-SDAG-NEXT: s_addc_u32 flat_scratch_hi, s11, 0
+; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s13
+; GFX9-SDAG-NEXT: s_addc_u32 s1, s1, 0
+; GFX9-SDAG-NEXT: s_mov_b64 s[10:11], s[8:9]
+; GFX9-SDAG-NEXT: s_getpc_b64 s[8:9]
+; GFX9-SDAG-NEXT: s_add_u32 s8, s8, callee at gotpcrel32@lo+4
+; GFX9-SDAG-NEXT: s_addc_u32 s9, s9, callee at gotpcrel32@hi+12
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX9-SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX9-SDAG-NEXT: v_or3_b32 v31, v0, v1, v2
-; GFX9-SDAG-NEXT: s_mov_b32 s12, s6
-; GFX9-SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s6
+; GFX9-SDAG-NEXT: s_mov_b64 s[8:9], s[6:7]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s12
; GFX9-SDAG-NEXT: s_mov_b32 s32, 0
; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT: s_swappc_b64 s[30:31], s[14:15]
@@ -100,27 +91,20 @@ define amdgpu_kernel void @caller() {
;
; GFX9-GISEL-LABEL: caller:
; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; GFX9-GISEL-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; GFX9-GISEL-NEXT: s_mov_b32 s38, -1
-; GFX9-GISEL-NEXT: s_mov_b32 s39, 0xe00000
-; GFX9-GISEL-NEXT: s_add_u32 s36, s36, s7
-; GFX9-GISEL-NEXT: s_addc_u32 s37, s37, 0
-; GFX9-GISEL-NEXT: s_add_u32 s8, s2, 36
-; GFX9-GISEL-NEXT: s_addc_u32 s9, s3, 0
-; GFX9-GISEL-NEXT: s_mov_b64 s[10:11], s[4:5]
-; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX9-GISEL-NEXT: s_getpc_b64 s[0:1]
-; GFX9-GISEL-NEXT: s_add_u32 s0, s0, callee at gotpcrel32@lo+4
-; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, callee at gotpcrel32@hi+12
-; GFX9-GISEL-NEXT: s_load_dwordx2 s[14:15], s[0:1], 0x0
+; GFX9-GISEL-NEXT: s_add_u32 flat_scratch_lo, s10, s13
+; GFX9-GISEL-NEXT: s_addc_u32 flat_scratch_hi, s11, 0
+; GFX9-GISEL-NEXT: s_add_u32 s0, s0, s13
+; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GFX9-GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
+; GFX9-GISEL-NEXT: s_getpc_b64 s[8:9]
+; GFX9-GISEL-NEXT: s_add_u32 s8, s8, callee at gotpcrel32@lo+4
+; GFX9-GISEL-NEXT: s_addc_u32 s9, s9, callee at gotpcrel32@hi+12
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX9-GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX9-GISEL-NEXT: v_or3_b32 v31, v0, v1, v2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9-GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
-; GFX9-GISEL-NEXT: s_mov_b32 s12, s6
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX9-GISEL-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX9-GISEL-NEXT: s_mov_b32 s32, 0
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: s_swappc_b64 s[30:31], s[14:15]
@@ -128,56 +112,44 @@ define amdgpu_kernel void @caller() {
;
; GFX9ARCH-SDAG-LABEL: caller:
; GFX9ARCH-SDAG: ; %bb.0:
-; GFX9ARCH-SDAG-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; GFX9ARCH-SDAG-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; GFX9ARCH-SDAG-NEXT: s_mov_b32 s38, -1
-; GFX9ARCH-SDAG-NEXT: s_mov_b32 s39, 0xe00000
-; GFX9ARCH-SDAG-NEXT: s_add_u32 s36, s36, s6
-; GFX9ARCH-SDAG-NEXT: s_addc_u32 s37, s37, 0
-; GFX9ARCH-SDAG-NEXT: s_add_u32 s8, s2, 36
-; GFX9ARCH-SDAG-NEXT: s_addc_u32 s9, s3, 0
-; GFX9ARCH-SDAG-NEXT: s_getpc_b64 s[2:3]
-; GFX9ARCH-SDAG-NEXT: s_add_u32 s2, s2, callee at gotpcrel32@lo+4
-; GFX9ARCH-SDAG-NEXT: s_addc_u32 s3, s3, callee at gotpcrel32@hi+12
-; GFX9ARCH-SDAG-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x0
-; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[10:11], s[4:5]
+; GFX9ARCH-SDAG-NEXT: s_add_u32 flat_scratch_lo, s10, s12
+; GFX9ARCH-SDAG-NEXT: s_addc_u32 flat_scratch_hi, s11, 0
+; GFX9ARCH-SDAG-NEXT: s_add_u32 s0, s0, s12
+; GFX9ARCH-SDAG-NEXT: s_addc_u32 s1, s1, 0
+; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[10:11], s[8:9]
+; GFX9ARCH-SDAG-NEXT: s_getpc_b64 s[8:9]
+; GFX9ARCH-SDAG-NEXT: s_add_u32 s8, s8, callee at gotpcrel32@lo+4
+; GFX9ARCH-SDAG-NEXT: s_addc_u32 s9, s9, callee at gotpcrel32@hi+12
+; GFX9ARCH-SDAG-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x0
; GFX9ARCH-SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9ARCH-SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX9ARCH-SDAG-NEXT: v_or3_b32 v31, v0, v1, v2
-; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
+; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9
; GFX9ARCH-SDAG-NEXT: s_mov_b32 s32, 0
; GFX9ARCH-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9ARCH-SDAG-NEXT: s_swappc_b64 s[30:31], s[6:7]
+; GFX9ARCH-SDAG-NEXT: s_swappc_b64 s[30:31], s[12:13]
; GFX9ARCH-SDAG-NEXT: s_endpgm
;
; GFX9ARCH-GISEL-LABEL: caller:
; GFX9ARCH-GISEL: ; %bb.0:
-; GFX9ARCH-GISEL-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; GFX9ARCH-GISEL-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; GFX9ARCH-GISEL-NEXT: s_mov_b32 s38, -1
-; GFX9ARCH-GISEL-NEXT: s_mov_b32 s39, 0xe00000
-; GFX9ARCH-GISEL-NEXT: s_add_u32 s36, s36, s6
-; GFX9ARCH-GISEL-NEXT: s_addc_u32 s37, s37, 0
-; GFX9ARCH-GISEL-NEXT: s_add_u32 s8, s2, 36
-; GFX9ARCH-GISEL-NEXT: s_addc_u32 s9, s3, 0
-; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[10:11], s[4:5]
-; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX9ARCH-GISEL-NEXT: s_getpc_b64 s[0:1]
-; GFX9ARCH-GISEL-NEXT: s_add_u32 s0, s0, callee at gotpcrel32@lo+4
-; GFX9ARCH-GISEL-NEXT: s_addc_u32 s1, s1, callee at gotpcrel32@hi+12
-; GFX9ARCH-GISEL-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0
+; GFX9ARCH-GISEL-NEXT: s_add_u32 flat_scratch_lo, s10, s12
+; GFX9ARCH-GISEL-NEXT: s_addc_u32 flat_scratch_hi, s11, 0
+; GFX9ARCH-GISEL-NEXT: s_add_u32 s0, s0, s12
+; GFX9ARCH-GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
+; GFX9ARCH-GISEL-NEXT: s_getpc_b64 s[8:9]
+; GFX9ARCH-GISEL-NEXT: s_add_u32 s8, s8, callee at gotpcrel32@lo+4
+; GFX9ARCH-GISEL-NEXT: s_addc_u32 s9, s9, callee at gotpcrel32@hi+12
+; GFX9ARCH-GISEL-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x0
; GFX9ARCH-GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX9ARCH-GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX9ARCH-GISEL-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, ttmp9
-; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX9ARCH-GISEL-NEXT: s_mov_b32 s32, 0
; GFX9ARCH-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9ARCH-GISEL-NEXT: s_swappc_b64 s[30:31], s[6:7]
+; GFX9ARCH-GISEL-NEXT: s_swappc_b64 s[30:31], s[12:13]
; GFX9ARCH-GISEL-NEXT: s_endpgm
;
; GFX12-SDAG-LABEL: caller:
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
index f9408cfd05267..4ee8b257d1e1a 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
@@ -1,38 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH-SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
define amdgpu_cs void @_amdgpu_cs_main() {
-; GFX9-LABEL: _amdgpu_cs_main:
-; GFX9: ; %bb.0: ; %.entry
-; GFX9-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
-; GFX9-NEXT: s_endpgm
-;
-; GFX9ARCH-SDAG-LABEL: _amdgpu_cs_main:
-; GFX9ARCH-SDAG: ; %bb.0: ; %.entry
-; GFX9ARCH-SDAG-NEXT: s_lshr_b32 s0, ttmp7, 16
-; GFX9ARCH-SDAG-NEXT: s_and_b32 s1, ttmp7, 0xffff
-; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9
-; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX9ARCH-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
-; GFX9ARCH-SDAG-NEXT: s_endpgm
-;
-; GFX9ARCH-GISEL-LABEL: _amdgpu_cs_main:
-; GFX9ARCH-GISEL: ; %bb.0: ; %.entry
-; GFX9ARCH-GISEL-NEXT: s_mov_b32 s0, ttmp9
-; GFX9ARCH-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff
-; GFX9ARCH-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16
-; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v2, s2
-; GFX9ARCH-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
-; GFX9ARCH-GISEL-NEXT: s_endpgm
-;
; GFX12-SDAG-LABEL: _amdgpu_cs_main:
; GFX12-SDAG: ; %bb.0: ; %.entry
; GFX12-SDAG-NEXT: s_and_b32 s0, ttmp7, 0xffff
@@ -67,65 +37,6 @@ define amdgpu_cs void @_amdgpu_cs_main() {
}
define amdgpu_cs void @caller() {
-; GFX9-LABEL: caller:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
-; GFX9-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
-; GFX9-NEXT: s_mov_b32 s10, -1
-; GFX9-NEXT: s_mov_b32 s11, 0xe00000
-; GFX9-NEXT: s_add_u32 s8, s8, s0
-; GFX9-NEXT: s_addc_u32 s9, s9, 0
-; GFX9-NEXT: s_getpc_b64 s[0:1]
-; GFX9-NEXT: s_add_u32 s0, s0, callee at gotpcrel32@lo+4
-; GFX9-NEXT: s_addc_u32 s1, s1, callee at gotpcrel32@hi+12
-; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX9-NEXT: s_mov_b64 s[0:1], s[8:9]
-; GFX9-NEXT: s_mov_b64 s[2:3], s[10:11]
-; GFX9-NEXT: s_mov_b32 s32, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX9-NEXT: s_endpgm
-;
-; GFX9ARCH-SDAG-LABEL: caller:
-; GFX9ARCH-SDAG: ; %bb.0:
-; GFX9ARCH-SDAG-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
-; GFX9ARCH-SDAG-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
-; GFX9ARCH-SDAG-NEXT: s_mov_b32 s10, -1
-; GFX9ARCH-SDAG-NEXT: s_mov_b32 s11, 0xe00000
-; GFX9ARCH-SDAG-NEXT: s_add_u32 s8, s8, s0
-; GFX9ARCH-SDAG-NEXT: s_addc_u32 s9, s9, 0
-; GFX9ARCH-SDAG-NEXT: s_getpc_b64 s[0:1]
-; GFX9ARCH-SDAG-NEXT: s_add_u32 s0, s0, callee at gotpcrel32@lo+4
-; GFX9ARCH-SDAG-NEXT: s_addc_u32 s1, s1, callee at gotpcrel32@hi+12
-; GFX9ARCH-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[0:1], s[8:9]
-; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[2:3], s[10:11]
-; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9
-; GFX9ARCH-SDAG-NEXT: s_mov_b32 s32, 0
-; GFX9ARCH-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9ARCH-SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX9ARCH-SDAG-NEXT: s_endpgm
-;
-; GFX9ARCH-GISEL-LABEL: caller:
-; GFX9ARCH-GISEL: ; %bb.0:
-; GFX9ARCH-GISEL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
-; GFX9ARCH-GISEL-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
-; GFX9ARCH-GISEL-NEXT: s_mov_b32 s10, -1
-; GFX9ARCH-GISEL-NEXT: s_mov_b32 s11, 0xe00000
-; GFX9ARCH-GISEL-NEXT: s_add_u32 s8, s8, s0
-; GFX9ARCH-GISEL-NEXT: s_addc_u32 s9, s9, 0
-; GFX9ARCH-GISEL-NEXT: s_getpc_b64 s[0:1]
-; GFX9ARCH-GISEL-NEXT: s_add_u32 s0, s0, callee at gotpcrel32@lo+4
-; GFX9ARCH-GISEL-NEXT: s_addc_u32 s1, s1, callee at gotpcrel32@hi+12
-; GFX9ARCH-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[0:1], s[8:9]
-; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, ttmp9
-; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[2:3], s[10:11]
-; GFX9ARCH-GISEL-NEXT: s_mov_b32 s32, 0
-; GFX9ARCH-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9ARCH-GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX9ARCH-GISEL-NEXT: s_endpgm
-;
; GFX12-SDAG-LABEL: caller:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9
@@ -151,43 +62,6 @@ define amdgpu_cs void @caller() {
declare amdgpu_gfx void @callee(i32)
define amdgpu_gfx void @workgroup_ids_gfx(ptr addrspace(1) %outx, ptr addrspace(1) %outy, ptr addrspace(1) %outz) {
-; GFX9-LABEL: workgroup_ids_gfx:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9ARCH-SDAG-LABEL: workgroup_ids_gfx:
-; GFX9ARCH-SDAG: ; %bb.0:
-; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v6, ttmp9
-; GFX9ARCH-SDAG-NEXT: s_and_b32 s34, ttmp7, 0xffff
-; GFX9ARCH-SDAG-NEXT: global_store_dword v[0:1], v6, off
-; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, s34
-; GFX9ARCH-SDAG-NEXT: s_lshr_b32 s34, ttmp7, 16
-; GFX9ARCH-SDAG-NEXT: global_store_dword v[2:3], v0, off
-; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, s34
-; GFX9ARCH-SDAG-NEXT: global_store_dword v[4:5], v0, off
-; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX9ARCH-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9ARCH-GISEL-LABEL: workgroup_ids_gfx:
-; GFX9ARCH-GISEL: ; %bb.0:
-; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v6, ttmp9
-; GFX9ARCH-GISEL-NEXT: s_and_b32 s34, ttmp7, 0xffff
-; GFX9ARCH-GISEL-NEXT: s_lshr_b32 s35, ttmp7, 16
-; GFX9ARCH-GISEL-NEXT: global_store_dword v[0:1], v6, off
-; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, s34
-; GFX9ARCH-GISEL-NEXT: global_store_dword v[2:3], v0, off
-; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, s35
-; GFX9ARCH-GISEL-NEXT: global_store_dword v[4:5], v0, off
-; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX9ARCH-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
; GFX12-LABEL: workgroup_ids_gfx:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
>From 66aa315da4fab2ba881c695a99103870324d21ab Mon Sep 17 00:00:00 2001
From: Weining Lu <luweining at loongson.cn>
Date: Wed, 29 May 2024 08:26:48 +0800
Subject: [PATCH 3/3] Use amdgcn-amd-amd{hsa,pal} for
lower-work-group-id-intrinsics-{hsa,pal}.ll respectively
---
.../lower-work-group-id-intrinsics-hsa.ll | 40 +++----
.../lower-work-group-id-intrinsics-pal.ll | 101 ++++++++++++++++++
2 files changed, 118 insertions(+), 23 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
index 22c6a24e9272d..1429251fc6421 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
@@ -3,6 +3,8 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-GISEL %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
define amdgpu_kernel void @workgroup_ids_kernel() {
; GFX9-LABEL: workgroup_ids_kernel:
@@ -152,29 +154,21 @@ define amdgpu_kernel void @caller() {
; GFX9ARCH-GISEL-NEXT: s_swappc_b64 s[30:31], s[12:13]
; GFX9ARCH-GISEL-NEXT: s_endpgm
;
-; GFX12-SDAG-LABEL: caller:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, ttmp9
-; GFX12-SDAG-NEXT: s_mov_b64 s[10:11], s[4:5]
-; GFX12-SDAG-NEXT: s_mov_b32 s7, callee at abs32@hi
-; GFX12-SDAG-NEXT: s_mov_b32 s6, callee at abs32@lo
-; GFX12-SDAG-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX12-SDAG-NEXT: s_mov_b64 s[8:9], s[2:3]
-; GFX12-SDAG-NEXT: s_mov_b32 s32, 0
-; GFX12-SDAG-NEXT: s_swappc_b64 s[30:31], s[6:7]
-; GFX12-SDAG-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: caller:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, ttmp9
-; GFX12-GISEL-NEXT: s_mov_b64 s[10:11], s[4:5]
-; GFX12-GISEL-NEXT: s_mov_b32 s6, callee at abs32@lo
-; GFX12-GISEL-NEXT: s_mov_b32 s7, callee at abs32@hi
-; GFX12-GISEL-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX12-GISEL-NEXT: s_mov_b64 s[8:9], s[2:3]
-; GFX12-GISEL-NEXT: s_mov_b32 s32, 0
-; GFX12-GISEL-NEXT: s_swappc_b64 s[30:31], s[6:7]
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: caller:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_mov_b64 s[10:11], s[4:5]
+; GFX12-NEXT: s_getpc_b64 s[4:5]
+; GFX12-NEXT: s_sext_i32_i16 s5, s5
+; GFX12-NEXT: s_add_co_u32 s4, s4, callee at gotpcrel32@lo+8
+; GFX12-NEXT: s_add_co_ci_u32 s5, s5, callee at gotpcrel32@hi+16
+; GFX12-NEXT: v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, ttmp9
+; GFX12-NEXT: s_load_b64 s[6:7], s[4:5], 0x0
+; GFX12-NEXT: s_mov_b64 s[4:5], s[0:1]
+; GFX12-NEXT: s_mov_b64 s[8:9], s[2:3]
+; GFX12-NEXT: s_mov_b32 s32, 0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_swappc_b64 s[30:31], s[6:7]
+; GFX12-NEXT: s_endpgm
%idx = call i32 @llvm.amdgcn.workgroup.id.x()
call void @callee(i32 %idx) #0
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
index 4ee8b257d1e1a..8009f917aef5a 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
@@ -1,8 +1,38 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH-SDAG %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
define amdgpu_cs void @_amdgpu_cs_main() {
+; GFX9-LABEL: _amdgpu_cs_main:
+; GFX9: ; %bb.0: ; %.entry
+; GFX9-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
+; GFX9-NEXT: s_endpgm
+;
+; GFX9ARCH-SDAG-LABEL: _amdgpu_cs_main:
+; GFX9ARCH-SDAG: ; %bb.0: ; %.entry
+; GFX9ARCH-SDAG-NEXT: s_lshr_b32 s0, ttmp7, 16
+; GFX9ARCH-SDAG-NEXT: s_and_b32 s1, ttmp7, 0xffff
+; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9
+; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX9ARCH-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
+; GFX9ARCH-SDAG-NEXT: s_endpgm
+;
+; GFX9ARCH-GISEL-LABEL: _amdgpu_cs_main:
+; GFX9ARCH-GISEL: ; %bb.0: ; %.entry
+; GFX9ARCH-GISEL-NEXT: s_mov_b32 s0, ttmp9
+; GFX9ARCH-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff
+; GFX9ARCH-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16
+; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX9ARCH-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
+; GFX9ARCH-GISEL-NEXT: s_endpgm
+;
; GFX12-SDAG-LABEL: _amdgpu_cs_main:
; GFX12-SDAG: ; %bb.0: ; %.entry
; GFX12-SDAG-NEXT: s_and_b32 s0, ttmp7, 0xffff
@@ -37,6 +67,40 @@ define amdgpu_cs void @_amdgpu_cs_main() {
}
define amdgpu_cs void @caller() {
+; GFX9ARCH-SDAG-LABEL: caller:
+; GFX9ARCH-SDAG: ; %bb.0:
+; GFX9ARCH-SDAG-NEXT: s_getpc_b64 s[8:9]
+; GFX9ARCH-SDAG-NEXT: s_mov_b32 s8, s0
+; GFX9ARCH-SDAG-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10
+; GFX9ARCH-SDAG-NEXT: s_mov_b32 s5, callee at abs32@hi
+; GFX9ARCH-SDAG-NEXT: s_mov_b32 s4, callee at abs32@lo
+; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9
+; GFX9ARCH-SDAG-NEXT: s_mov_b32 s32, 0
+; GFX9ARCH-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9ARCH-SDAG-NEXT: s_add_u32 s8, s8, s0
+; GFX9ARCH-SDAG-NEXT: s_addc_u32 s9, s9, 0
+; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[0:1], s[8:9]
+; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[2:3], s[10:11]
+; GFX9ARCH-SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
+; GFX9ARCH-SDAG-NEXT: s_endpgm
+;
+; GFX9ARCH-GISEL-LABEL: caller:
+; GFX9ARCH-GISEL: ; %bb.0:
+; GFX9ARCH-GISEL-NEXT: s_getpc_b64 s[8:9]
+; GFX9ARCH-GISEL-NEXT: s_mov_b32 s8, s0
+; GFX9ARCH-GISEL-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10
+; GFX9ARCH-GISEL-NEXT: s_mov_b32 s4, callee at abs32@lo
+; GFX9ARCH-GISEL-NEXT: s_mov_b32 s5, callee at abs32@hi
+; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, ttmp9
+; GFX9ARCH-GISEL-NEXT: s_mov_b32 s32, 0
+; GFX9ARCH-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9ARCH-GISEL-NEXT: s_add_u32 s8, s8, s0
+; GFX9ARCH-GISEL-NEXT: s_addc_u32 s9, s9, 0
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[0:1], s[8:9]
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[2:3], s[10:11]
+; GFX9ARCH-GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
+; GFX9ARCH-GISEL-NEXT: s_endpgm
+;
; GFX12-SDAG-LABEL: caller:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9
@@ -62,6 +126,43 @@ define amdgpu_cs void @caller() {
declare amdgpu_gfx void @callee(i32)
define amdgpu_gfx void @workgroup_ids_gfx(ptr addrspace(1) %outx, ptr addrspace(1) %outy, ptr addrspace(1) %outz) {
+; GFX9-LABEL: workgroup_ids_gfx:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9ARCH-SDAG-LABEL: workgroup_ids_gfx:
+; GFX9ARCH-SDAG: ; %bb.0:
+; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v6, ttmp9
+; GFX9ARCH-SDAG-NEXT: s_and_b32 s34, ttmp7, 0xffff
+; GFX9ARCH-SDAG-NEXT: global_store_dword v[0:1], v6, off
+; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, s34
+; GFX9ARCH-SDAG-NEXT: s_lshr_b32 s34, ttmp7, 16
+; GFX9ARCH-SDAG-NEXT: global_store_dword v[2:3], v0, off
+; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, s34
+; GFX9ARCH-SDAG-NEXT: global_store_dword v[4:5], v0, off
+; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9ARCH-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9ARCH-GISEL-LABEL: workgroup_ids_gfx:
+; GFX9ARCH-GISEL: ; %bb.0:
+; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v6, ttmp9
+; GFX9ARCH-GISEL-NEXT: s_and_b32 s34, ttmp7, 0xffff
+; GFX9ARCH-GISEL-NEXT: s_lshr_b32 s35, ttmp7, 16
+; GFX9ARCH-GISEL-NEXT: global_store_dword v[0:1], v6, off
+; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, s34
+; GFX9ARCH-GISEL-NEXT: global_store_dword v[2:3], v0, off
+; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, s35
+; GFX9ARCH-GISEL-NEXT: global_store_dword v[4:5], v0, off
+; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9ARCH-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: workgroup_ids_gfx:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
More information about the llvm-commits
mailing list