[llvm] [ARM64EC] Warn on using disallowed registers in assembly src. (PR #93618)
Namish Kukreja via llvm-commits
llvm-commits at lists.llvm.org
Tue May 28 15:15:54 PDT 2024
https://github.com/namikukr created https://github.com/llvm/llvm-project/pull/93618
ARM64EC designates a set of disallowed registers, because a mapping does not exist from them to x64. The MSVC assembler (armasm64) has a warning for this.
A test is also included as part of the patch.
See the list of disallowed registers below:
https://learn.microsoft.com/en-us/cpp/build/arm64ec-windows-abi-conventions?view=msvc-170#register-mapping
>From 3c9ea0db8484e8fc2bdf4350ae09b3eb8d95b3a4 Mon Sep 17 00:00:00 2001
From: Namish Kukreja <namikukr at quicinc.com>
Date: Wed, 22 May 2024 15:44:35 -0700
Subject: [PATCH] [ARM64EC] Warn on using disallowed registers in assembly src.
ARM64EC designates a set of disallowed registers, because
a mapping does not exist from them to x64. The MSVC assembler
(armasm64) has a warning for this.
A test is also included as part of the patch.
See the list of disallowed registers below:
https://learn.microsoft.com/en-us/cpp/build/arm64ec-windows-abi-conventions?view=msvc-170#register-mapping
---
.../AArch64/AsmParser/AArch64AsmParser.cpp | 27 +++++++
.../test/MC/AArch64/arm64ec-disallowed-regs.s | 75 +++++++++++++++++++
2 files changed, 102 insertions(+)
create mode 100644 llvm/test/MC/AArch64/arm64ec-disallowed-regs.s
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 13a68b7dcf984..ea329dd71e398 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -294,11 +294,13 @@ class AArch64AsmParser : public MCTargetAsmParser {
#include "AArch64GenAsmMatcher.inc"
};
bool IsILP32;
+ bool IsWindowsArm64EC;
AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI, MII) {
IsILP32 = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32;
+ IsWindowsArm64EC = STI.getTargetTriple().isWindowsArm64EC();
MCAsmParserExtension::Initialize(Parser);
MCStreamer &S = getParser().getStreamer();
if (S.getTargetStreamer() == nullptr)
@@ -5315,6 +5317,31 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
}
}
+ // On ARM64EC, only valid registers may be used. Warn against using
+ // explicitly disallowed registers.
+ if (IsWindowsArm64EC) {
+ for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
+ if (Inst.getOperand(i).isReg()) {
+ unsigned Reg = Inst.getOperand(i).getReg();
+ // At this point, vector registers are matched to their
+ // appropriately sized alias.
+ if ((Reg == AArch64::W13 || Reg == AArch64::X13) ||
+ (Reg == AArch64::W14 || Reg == AArch64::X14) ||
+ (Reg == AArch64::W23 || Reg == AArch64::X23) ||
+ (Reg == AArch64::W24 || Reg == AArch64::X24) ||
+ (Reg == AArch64::W28 || Reg == AArch64::X28) ||
+ (Reg >= AArch64::Q16 && Reg <= AArch64::Q31) ||
+ (Reg >= AArch64::D16 && Reg <= AArch64::D31) ||
+ (Reg >= AArch64::S16 && Reg <= AArch64::S31) ||
+ (Reg >= AArch64::H16 && Reg <= AArch64::H31) ||
+ (Reg >= AArch64::B16 && Reg <= AArch64::B31)) {
+ Warning(IDLoc, "this instruction uses disallowed registers.");
+ break;
+ }
+ }
+ }
+ }
+
// Check for indexed addressing modes w/ the base register being the
// same as a destination/source register or pair load where
// the Rt == Rt2. All of those are undefined behaviour.
diff --git a/llvm/test/MC/AArch64/arm64ec-disallowed-regs.s b/llvm/test/MC/AArch64/arm64ec-disallowed-regs.s
new file mode 100644
index 0000000000000..8061987a51998
--- /dev/null
+++ b/llvm/test/MC/AArch64/arm64ec-disallowed-regs.s
@@ -0,0 +1,75 @@
+// RUN: llvm-mc -triple arm64ec-pc-windows-msvc < %s 2> %t.log
+// RUN: FileCheck %s --check-prefix=CHECK-ERR < %t.log
+
+
+// ---- disallowed x registers ----
+orr x13, x0, x1 // x13
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orr x14, x2, x3 // x14
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orr x4, x23, x5 // x23
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orr x6, x7, x24 // x24
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orr x28, x8, x9 // x28
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+
+// ---- disallowed w registers ----
+orr w0, w13, w1 // w13
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orr w14, w2, w3 // w14
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orr w4, w23, w5 // w23
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orr w6, w7, w24 // w24
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orr w28, w8, w9 // w28
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+
+// ---- disallowed vector registers ----
+orn v1.8b, v16.8b, v2.8b // v16
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v2.16b, v17.16b, v3.16b // v17
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v3.8b, v18.8b, v4.8b // v18
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v4.16b, v19.16b, v5.16b // v19
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v5.8b, v20.8b, v6.8b // v20
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v21.8b, v6.8b, v7.8b // v21
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v7.16b, v8.16b, v22.16b // v22
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v23.8b, v8.8b, v9.8b // v23
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v9.16b, v24.16b, v10.16b // v24
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v10.8b, v25.8b, v11.8b // v25
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v11.8b, v12.8b, v26.8b // v26
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v12.8b, v27.8b, v13.8b // v27
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v13.16b, v28.16b, v14.16b // v28
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v14.8b, v29.8b, v15.8b // v29
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v15.8b, v30.8b, v15.8b // v30
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+orn v1.16b, v31.16b, v1.16b // v31
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+
+// ---- random tests on h, b, d, s registers ----
+orn.16b v1, v16, v2
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+mov.4h v17, v8
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+fmul.2s v2, v18, v11
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+clz.8h v3, v19
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+add.4s v0, v20, v1
+// CHECK-ERR: warning: this instruction uses disallowed registers.
+add.2d v0, v20, v1
+// CHECK-ERR: warning: this instruction uses disallowed registers.
\ No newline at end of file
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