[llvm] 98fa0f6 - DAG: Handle vector splitting for fminnum_ieee/fmaxnum_ieee

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2024-05-28T22:58:24+02:00
New Revision: 98fa0f6981f33b7d8f5aa38babc1e71bc0209de8

URL: https://github.com/llvm/llvm-project/commit/98fa0f6981f33b7d8f5aa38babc1e71bc0209de8
DIFF: https://github.com/llvm/llvm-project/commit/98fa0f6981f33b7d8f5aa38babc1e71bc0209de8.diff

LOG: DAG: Handle vector splitting for fminnum_ieee/fmaxnum_ieee

Avoids regression in future commit which starts producing
illegal instances.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 14e8708fd3f38..361416edb554c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1174,8 +1174,12 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::FADD: case ISD::VP_FADD:
   case ISD::FSUB: case ISD::VP_FSUB:
   case ISD::FMUL: case ISD::VP_FMUL:
-  case ISD::FMINNUM: case ISD::VP_FMINNUM:
-  case ISD::FMAXNUM: case ISD::VP_FMAXNUM:
+  case ISD::FMINNUM:
+  case ISD::FMINNUM_IEEE:
+  case ISD::VP_FMINNUM:
+  case ISD::FMAXNUM:
+  case ISD::FMAXNUM_IEEE:
+  case ISD::VP_FMAXNUM:
   case ISD::FMINIMUM:
   case ISD::VP_FMINIMUM:
   case ISD::FMAXIMUM: