[llvm] [SelectionDAG] Add support for the 3-way comparison intrinsics [US]CMP (PR #91871)
via llvm-commits
llvm-commits at lists.llvm.org
Tue May 28 13:07:24 PDT 2024
https://github.com/Poseydon42 updated https://github.com/llvm/llvm-project/pull/91871
>From 81dfa5432dd76f27fe2a7993f57aa653b530918b Mon Sep 17 00:00:00 2001
From: Poseydon42 <vvmposeydon at gmail.com>
Date: Sat, 11 May 2024 23:33:14 +0100
Subject: [PATCH 1/2] [SelectionDAG] Add support for the 3-way comparison
intrinsics [US]CMP
---
llvm/include/llvm/CodeGen/ISDOpcodes.h | 6 +
llvm/include/llvm/CodeGen/TargetLowering.h | 4 +
.../include/llvm/Target/TargetSelectionDAG.td | 5 +
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 6 +
.../SelectionDAG/LegalizeIntegerTypes.cpp | 41 ++++++
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 5 +
.../SelectionDAG/SelectionDAGBuilder.cpp | 16 +++
.../SelectionDAG/SelectionDAGDumper.cpp | 2 +
.../CodeGen/SelectionDAG/TargetLowering.cpp | 21 +++
llvm/lib/CodeGen/TargetLoweringBase.cpp | 3 +
llvm/test/CodeGen/X86/uscmp.ll | 129 ++++++++++++++++++
11 files changed, 238 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/uscmp.ll
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 6429947958ee9..7d36f582244b0 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -677,6 +677,12 @@ enum NodeType {
UMIN,
UMAX,
+ /// [US]CMP - 3-way comparison of signed or unsigned integers. Returns -1, 0,
+ /// or 1 depending on whether Op0 <, ==, or > Op1. The operands can have type
+ /// different to the result.
+ SCMP,
+ UCMP,
+
/// Bitwise operators - logical and, logical or, logical xor.
AND,
OR,
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 7ed08cfa8a202..82c450afcbcf6 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5402,6 +5402,10 @@ class TargetLowering : public TargetLoweringBase {
/// method accepts integers as its arguments.
SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
+ /// Method for building the DAG expansion of ISD::[US]CMP. This
+ /// method accepts integers as its arguments
+ SDValue expandCMP(SDNode *Node, SelectionDAG &DAG) const;
+
/// Method for building the DAG expansion of ISD::[US]SHLSAT. This
/// method accepts integers as its arguments.
SDValue expandShlSat(SDNode *Node, SelectionDAG &DAG) const;
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 1684b424e3b44..6d771521aa739 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -434,6 +434,11 @@ def umin : SDNode<"ISD::UMIN" , SDTIntBinOp,
def umax : SDNode<"ISD::UMAX" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
+def scmp : SDNode<"ISD::SCMP" , SDTIntBinOp,
+ []>;
+def ucmp : SDNode<"ISD::UCMP" , SDTIntBinOp,
+ []>;
+
def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
def ssubsat : SDNode<"ISD::SSUBSAT" , SDTIntBinOp>;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index bfc3e08c1632d..f7da195e03bd1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1148,6 +1148,8 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
case ISD::USUBSAT:
case ISD::SSHLSAT:
case ISD::USHLSAT:
+ case ISD::SCMP:
+ case ISD::UCMP:
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
@@ -3864,6 +3866,10 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
case ISD::USUBSAT:
Results.push_back(TLI.expandAddSubSat(Node, DAG));
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Results.push_back(TLI.expandCMP(Node, DAG));
+ break;
case ISD::SSHLSAT:
case ISD::USHLSAT:
Results.push_back(TLI.expandShlSat(Node, DAG));
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 0aa36deda79dc..e82ab9db4c090 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -232,6 +232,11 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
Res = PromoteIntRes_ADDSUBSHLSAT<VPMatchContext>(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = PromoteIntRes_CMP(N);
+ break;
+
case ISD::SMULFIX:
case ISD::SMULFIXSAT:
case ISD::UMULFIX:
@@ -1246,6 +1251,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
return Res;
}
+SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
+ EVT PromotedResultTy =
+ TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+ return DAG.getNode(N->getOpcode(), SDLoc(N), PromotedResultTy,
+ N->getOperand(0), N->getOperand(1));
+}
+
SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
SDValue Mask = N->getOperand(0);
@@ -1874,6 +1886,9 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::ROTL:
case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
+ case ISD::SCMP:
+ case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
+
case ISD::FSHL:
case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
@@ -2184,6 +2199,17 @@ SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
ZExtPromotedInteger(N->getOperand(1))), 0);
}
+SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
+ SDValue LHS = N->getOpcode() == ISD::UCMP
+ ? ZExtPromotedInteger(N->getOperand(0))
+ : SExtPromotedInteger(N->getOperand(0));
+ SDValue RHS = N->getOpcode() == ISD::UCMP
+ ? ZExtPromotedInteger(N->getOperand(1))
+ : SExtPromotedInteger(N->getOperand(1));
+
+ return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS), 0);
+}
+
SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
ZExtPromotedInteger(N->getOperand(2))), 0);
@@ -2741,6 +2767,9 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::UMIN:
case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
+ case ISD::SCMP:
+ case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
+
case ISD::ADD:
case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
@@ -3233,6 +3262,11 @@ void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
SplitInteger(Result, Lo, Hi);
}
+void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
+ SDValue ExpandedCMP = TLI.expandCMP(N, DAG);
+ SplitInteger(ExpandedCMP, Lo, Hi);
+}
+
void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
SDValue &Lo, SDValue &Hi) {
SDLoc dl(N);
@@ -5137,6 +5171,9 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::RETURNADDR:
case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
+ case ISD::SCMP:
+ case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
+
case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
case ISD::STACKMAP:
Res = ExpandIntOp_STACKMAP(N, OpNo);
@@ -5398,6 +5435,10 @@ SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
}
+SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
+ return TLI.expandCMP(N, DAG);
+}
+
SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
// The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
// surely makes pretty nice problems on 8/16 bit targets. Just truncate this
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 4b06e19656ce6..035f16720c3f6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -324,6 +324,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntRes_Overflow(SDNode *N);
SDValue PromoteIntRes_FFREXP(SDNode *N);
SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
+ SDValue PromoteIntRes_CMP(SDNode *N);
SDValue PromoteIntRes_Select(SDNode *N);
SDValue PromoteIntRes_SELECT_CC(SDNode *N);
SDValue PromoteIntRes_SETCC(SDNode *N);
@@ -375,6 +376,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_Shift(SDNode *N);
+ SDValue PromoteIntOp_CMP(SDNode *N);
SDValue PromoteIntOp_FunnelShift(SDNode *N);
SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
SDValue PromoteIntOp_VP_SIGN_EXTEND(SDNode *N);
@@ -457,6 +459,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void ExpandIntRes_MINMAX (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_CMP (SDNode *N, SDValue &Lo, SDValue &Hi);
+
void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
@@ -485,6 +489,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ExpandIntOp_SETCC(SDNode *N);
SDValue ExpandIntOp_SETCCCARRY(SDNode *N);
SDValue ExpandIntOp_Shift(SDNode *N);
+ SDValue ExpandIntOp_CMP(SDNode *N);
SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
SDValue ExpandIntOp_TRUNCATE(SDNode *N);
SDValue ExpandIntOp_XINT_TO_FP(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index cfd82a342433f..16d8a9816b013 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7143,6 +7143,22 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
setValue(&I, DAG.getNode(ISD::ABS, sdl, Op1.getValueType(), Op1));
return;
}
+ case Intrinsic::scmp: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
+ I.getType());
+ setValue(&I, DAG.getNode(ISD::SCMP, sdl, DestVT, Op1, Op2));
+ break;
+ }
+ case Intrinsic::ucmp: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
+ I.getType());
+ setValue(&I, DAG.getNode(ISD::UCMP, sdl, DestVT, Op1, Op2));
+ break;
+ }
case Intrinsic::stacksave: {
SDValue Op = getRoot();
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index 4ad4a938ca97f..d5e8256aa4085 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -289,6 +289,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::SMAX: return "smax";
case ISD::UMIN: return "umin";
case ISD::UMAX: return "umax";
+ case ISD::SCMP: return "scmp";
+ case ISD::UCMP: return "ucmp";
case ISD::FLDEXP: return "fldexp";
case ISD::STRICT_FLDEXP: return "strict_fldexp";
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 336d89fbcf638..3de57001135e9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -10274,6 +10274,27 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
return DAG.getSelect(dl, VT, Overflow, Result, SumDiff);
}
+SDValue TargetLowering::expandCMP(SDNode *Node, SelectionDAG &DAG) const {
+ unsigned Opcode = Node->getOpcode();
+ SDValue LHS = Node->getOperand(0);
+ SDValue RHS = Node->getOperand(1);
+ EVT VT = LHS.getValueType();
+ EVT ResVT = Node->getValueType(0);
+ EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ SDLoc dl(Node);
+
+ auto LTPredicate = (Opcode == ISD::UCMP ? ISD::SETULT : ISD::SETLT);
+ auto GTPredicate = (Opcode == ISD::UCMP ? ISD::SETUGT : ISD::SETGT);
+
+ SDValue IsLT = DAG.getSetCC(dl, BoolVT, LHS, RHS, LTPredicate);
+ SDValue IsGT = DAG.getSetCC(dl, BoolVT, LHS, RHS, GTPredicate);
+ SDValue SelectZeroOrOne =
+ DAG.getSelect(dl, ResVT, IsGT, DAG.getConstant(1, dl, ResVT),
+ DAG.getConstant(0, dl, ResVT));
+ return DAG.getSelect(dl, ResVT, IsLT, DAG.getConstant(-1, dl, ResVT),
+ SelectZeroOrOne);
+}
+
SDValue TargetLowering::expandShlSat(SDNode *Node, SelectionDAG &DAG) const {
unsigned Opcode = Node->getOpcode();
bool IsSigned = Opcode == ISD::SSHLSAT;
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 6e7b67ded23c8..311ba68b96ec9 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -909,6 +909,9 @@ void TargetLoweringBase::initActions() {
setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
Expand);
+ // [US]CMP default to expand
+ setOperationAction({ISD::UCMP, ISD::SCMP}, VT, Expand);
+
// Halving adds
setOperationAction(
{ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT,
diff --git a/llvm/test/CodeGen/X86/uscmp.ll b/llvm/test/CodeGen/X86/uscmp.ll
new file mode 100644
index 0000000000000..3d1765b94f72a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/uscmp.ll
@@ -0,0 +1,129 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define i8 @ucmp(i32 %x, i32 %y) {
+; CHECK-LABEL: ucmp:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
+ ret i8 %1
+}
+
+define i8 @scmp(i32 %x, i32 %y) {
+; CHECK-LABEL: scmp:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
+ ret i8 %1
+}
+
+define i4 @ucmp_narrow_result(i32 %x, i32 %y) {
+; CHECK-LABEL: ucmp_narrow_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i4 @llvm.ucmp(i32 %x, i32 %y)
+ ret i4 %1
+}
+
+define i8 @scmp_narrow_op(i5 %x, i5 %y) {
+; CHECK-LABEL: scmp_narrow_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andb $31, %sil
+; CHECK-NEXT: andb $31, %dil
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpb %sil, %dil
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.ucmp(i5 %x, i5 %y)
+ ret i8 %1
+}
+
+define i128 @ucmp_wide_result(i32 %x, i32 %y) {
+; CHECK-LABEL: ucmp_wide_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaeq %rcx, %rax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: retq
+ %1 = call i128 @llvm.ucmp(i32 %x, i32 %y)
+ ret i128 %1
+}
+
+define i8 @scmp_wide_op(i128 %x, i128 %y) {
+; CHECK-LABEL: scmp_wide_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmpq %rdi, %rdx
+; CHECK-NEXT: movq %rcx, %rax
+; CHECK-NEXT: sbbq %rsi, %rax
+; CHECK-NEXT: setl %al
+; CHECK-NEXT: movzbl %al, %r8d
+; CHECK-NEXT: cmpq %rdx, %rdi
+; CHECK-NEXT: sbbq %rcx, %rsi
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovgel %r8d, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.scmp(i128 %x, i128 %y)
+ ret i8 %1
+}
+
+define i41 @ucmp_uncommon_types(i7 %x, i7 %y) {
+; CHECK-LABEL: ucmp_uncommon_types:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andb $127, %sil
+; CHECK-NEXT: andb $127, %dil
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpb %sil, %dil
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaeq %rcx, %rax
+; CHECK-NEXT: retq
+ %1 = call i41 @llvm.ucmp(i7 %x, i7 %y)
+ ret i41 %1
+}
+
+define i125 @scmp_uncommon_types(i99 %x, i99 %y) {
+; CHECK-LABEL: scmp_uncommon_types:
+; CHECK: # %bb.0:
+; CHECK-NEXT: shlq $29, %rsi
+; CHECK-NEXT: sarq $29, %rsi
+; CHECK-NEXT: shlq $29, %rcx
+; CHECK-NEXT: sarq $29, %rcx
+; CHECK-NEXT: cmpq %rdi, %rdx
+; CHECK-NEXT: movq %rcx, %rax
+; CHECK-NEXT: sbbq %rsi, %rax
+; CHECK-NEXT: setl %al
+; CHECK-NEXT: movzbl %al, %r8d
+; CHECK-NEXT: cmpq %rdx, %rdi
+; CHECK-NEXT: sbbq %rcx, %rsi
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovgeq %r8, %rax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: retq
+ %1 = call i125 @llvm.scmp(i99 %x, i99 %y)
+ ret i125 %1
+}
>From 580c2820b64aa838a9e81606a565aa9c04b25718 Mon Sep 17 00:00:00 2001
From: Poseydon42 <vvmposeydon at gmail.com>
Date: Thu, 16 May 2024 22:22:44 +0100
Subject: [PATCH 2/2] [SelectionDAG] Properly handle legalization of vector
types for [US]CMP nodes
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 5 +
.../SelectionDAG/LegalizeVectorOps.cpp | 2 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 142 +++
.../SelectionDAG/SelectionDAGBuilder.cpp | 6 +-
llvm/test/CodeGen/X86/scmp.ll | 794 +++++++++++++
llvm/test/CodeGen/X86/ucmp.ll | 1010 +++++++++++++++++
llvm/test/CodeGen/X86/uscmp.ll | 129 ---
7 files changed, 1955 insertions(+), 133 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/scmp.ll
create mode 100644 llvm/test/CodeGen/X86/ucmp.ll
delete mode 100644 llvm/test/CodeGen/X86/uscmp.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 035f16720c3f6..74ab2f44149fa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -784,6 +784,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void ScalarizeVectorResult(SDNode *N, unsigned ResNo);
SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
SDValue ScalarizeVecRes_BinOp(SDNode *N);
+ SDValue ScalarizeVecRes_CMP(SDNode *N);
SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
SDValue ScalarizeVecRes_StrictFPOp(SDNode *N);
@@ -857,6 +858,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void SplitVectorResult(SDNode *N, unsigned ResNo);
void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_FFREXP(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi);
void SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi);
@@ -920,6 +922,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SplitVecOp_VSETCC(SDNode *N);
SDValue SplitVecOp_FP_ROUND(SDNode *N);
SDValue SplitVecOp_FPOpDifferentTypes(SDNode *N);
+ SDValue SplitVecOp_CMP(SDNode *N);
SDValue SplitVecOp_FP_TO_XINT_SAT(SDNode *N);
SDValue SplitVecOp_VP_CttzElements(SDNode *N);
@@ -987,6 +990,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue WidenVecRes_Ternary(SDNode *N);
SDValue WidenVecRes_Binary(SDNode *N);
+ SDValue WidenVecRes_CMP(SDNode *N);
SDValue WidenVecRes_BinaryCanTrap(SDNode *N);
SDValue WidenVecRes_BinaryWithExtraScalarOp(SDNode *N);
SDValue WidenVecRes_StrictFP(SDNode *N);
@@ -1006,6 +1010,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue WidenVecOp_BITCAST(SDNode *N);
SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
SDValue WidenVecOp_EXTEND(SDNode *N);
+ SDValue WidenVecOp_CMP(SDNode *N);
SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue WidenVecOp_INSERT_SUBVECTOR(SDNode *N);
SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 423df9ae6b2a5..3a1c11da24075 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -442,6 +442,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
case ISD::MGATHER:
+ case ISD::SCMP:
+ case ISD::UCMP:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
break;
case ISD::SMULFIX:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index cab4dc5f3c156..0fe6e9e0252a4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -164,6 +164,12 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::ROTR:
R = ScalarizeVecRes_BinOp(N);
break;
+
+ case ISD::SCMP:
+ case ISD::UCMP:
+ R = ScalarizeVecRes_CMP(N);
+ break;
+
case ISD::FMA:
case ISD::FSHL:
case ISD::FSHR:
@@ -213,6 +219,27 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
LHS.getValueType(), LHS, RHS, N->getFlags());
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_CMP(SDNode *N) {
+ SDLoc DL(N);
+
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ if (getTypeAction(LHS.getValueType()) ==
+ TargetLowering::TypeScalarizeVector) {
+ LHS = GetScalarizedVector(LHS);
+ RHS = GetScalarizedVector(RHS);
+ } else {
+ EVT VT = LHS.getValueType().getVectorElementType();
+ LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
+ DAG.getVectorIdxConstant(0, DL));
+ RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
+ DAG.getVectorIdxConstant(0, DL));
+ }
+
+ return DAG.getNode(N->getOpcode(), SDLoc(N),
+ N->getValueType(0).getVectorElementType(), LHS, RHS);
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
SDValue Op0 = GetScalarizedVector(N->getOperand(0));
SDValue Op1 = GetScalarizedVector(N->getOperand(1));
@@ -1184,6 +1211,10 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
SplitVecRes_TernaryOp(N, Lo, Hi);
break;
+ case ISD::SCMP: case ISD::UCMP:
+ SplitVecRes_CMP(N, Lo, Hi);
+ break;
+
#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
case ISD::STRICT_##DAGN:
#include "llvm/IR/ConstrainedOps.def"
@@ -1327,6 +1358,21 @@ void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
{Op0Hi, Op1Hi, Op2Hi, MaskHi, EVLHi}, Flags);
}
+void DAGTypeLegalizer::SplitVecRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ EVT SplitResVT = N->getValueType(0).getHalfNumVectorElementsVT(Ctxt);
+
+ auto [LHSLo, LHSHi] = DAG.SplitVector(LHS, dl);
+ auto [RHSLo, RHSHi] = DAG.SplitVector(RHS, dl);
+
+ Lo = DAG.getNode(N->getOpcode(), dl, SplitResVT, LHSLo, RHSLo);
+ Hi = DAG.getNode(N->getOpcode(), dl, SplitResVT, LHSHi, RHSHi);
+}
+
void DAGTypeLegalizer::SplitVecRes_FIX(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue LHSLo, LHSHi;
GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
@@ -3054,6 +3100,11 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
Res = SplitVecOp_FPOpDifferentTypes(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = SplitVecOp_CMP(N);
+ break;
+
case ISD::ANY_EXTEND_VECTOR_INREG:
case ISD::SIGN_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
@@ -4043,6 +4094,25 @@ SDValue DAGTypeLegalizer::SplitVecOp_FPOpDifferentTypes(SDNode *N) {
return DAG.getNode(ISD::CONCAT_VECTORS, DL, N->getValueType(0), Lo, Hi);
}
+SDValue DAGTypeLegalizer::SplitVecOp_CMP(SDNode *N) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHSLo, LHSHi, RHSLo, RHSHi;
+ GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
+ GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
+
+ EVT ResVT = N->getValueType(0);
+ ElementCount SplitOpEC = LHSLo.getValueType().getVectorElementCount();
+ EVT NewResVT =
+ EVT::getVectorVT(Ctxt, ResVT.getVectorElementType(), SplitOpEC);
+
+ SDValue Lo = DAG.getNode(N->getOpcode(), dl, NewResVT, LHSLo, RHSLo);
+ SDValue Hi = DAG.getNode(N->getOpcode(), dl, NewResVT, LHSHi, RHSHi);
+
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
+}
+
SDValue DAGTypeLegalizer::SplitVecOp_FP_TO_XINT_SAT(SDNode *N) {
EVT ResVT = N->getValueType(0);
SDValue Lo, Hi;
@@ -4220,6 +4290,11 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
Res = WidenVecRes_Binary(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = WidenVecRes_CMP(N);
+ break;
+
case ISD::FPOW:
case ISD::FREM:
if (unrollExpandedOp())
@@ -4426,6 +4501,42 @@ SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
{InOp1, InOp2, Mask, N->getOperand(3)}, N->getFlags());
}
+SDValue DAGTypeLegalizer::WidenVecRes_CMP(SDNode *N) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ EVT OpVT = LHS.getValueType();
+ EVT OpElementVT = OpVT.getVectorElementType();
+ EVT TransformedOpVT = TLI.getTypeToTransformTo(Ctxt, OpVT);
+ if (TransformedOpVT.getVectorNumElements() > OpVT.getVectorNumElements()) {
+ LHS = GetWidenedVector(LHS);
+ RHS = GetWidenedVector(RHS);
+ }
+
+ EVT WidenResVT = TLI.getTypeToTransformTo(Ctxt, N->getValueType(0));
+ ElementCount WidenResEC = WidenResVT.getVectorElementCount();
+ EVT WidenResElementVT = WidenResVT.getVectorElementType();
+
+ SDValue CMP = DAG.getNode(N->getOpcode(), dl, LHS.getValueType(), LHS, RHS);
+
+ EVT WideUndefVectorVT = EVT::getVectorVT(Ctxt, OpElementVT, WidenResEC);
+ SDValue WideUndefValue = DAG.getUNDEF(WideUndefVectorVT);
+
+ SDValue WideResult =
+ DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideUndefVectorVT, WideUndefValue,
+ CMP, DAG.getVectorIdxConstant(0, dl));
+
+ ISD::NodeType ExtendCode;
+ if (OpElementVT.getSizeInBits() > WidenResElementVT.getSizeInBits()) {
+ ExtendCode = ISD::TRUNCATE;
+ } else {
+ ExtendCode = (N->getOpcode() == ISD::SCMP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND);
+ }
+ return DAG.getNode(ExtendCode, dl, WidenResVT, WideResult);
+}
+
SDValue DAGTypeLegalizer::WidenVecRes_BinaryWithExtraScalarOp(SDNode *N) {
// Binary op widening, but with an extra operand that shouldn't be widened.
SDLoc dl(N);
@@ -6129,6 +6240,11 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
Res = WidenVecOp_EXTEND(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = WidenVecOp_CMP(N);
+ break;
+
case ISD::FP_EXTEND:
case ISD::STRICT_FP_EXTEND:
case ISD::FP_ROUND:
@@ -6273,6 +6389,32 @@ SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
}
}
+SDValue DAGTypeLegalizer::WidenVecOp_CMP(SDNode *N) {
+ SDLoc dl(N);
+
+ EVT OpVT = N->getOperand(0).getValueType();
+ EVT ResVT = N->getValueType(0);
+ SDValue LHS = GetWidenedVector(N->getOperand(0));
+ SDValue RHS = GetWidenedVector(N->getOperand(1));
+
+ // 1. EXTRACT_SUBVECTOR
+ // 2. SIGN_EXTEND/ZERO_EXTEND
+ // 3. CMP
+ LHS = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, LHS,
+ DAG.getVectorIdxConstant(0, dl));
+ RHS = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, RHS,
+ DAG.getVectorIdxConstant(0, dl));
+
+ // At this point the result type is guaranteed to be valid, so we can use it
+ // as the operand type by extending it appropriately
+ ISD::NodeType ExtendOpcode =
+ N->getOpcode() == ISD::SCMP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+ LHS = DAG.getNode(ExtendOpcode, dl, ResVT, LHS);
+ RHS = DAG.getNode(ExtendOpcode, dl, ResVT, RHS);
+
+ return DAG.getNode(N->getOpcode(), dl, ResVT, LHS, RHS);
+}
+
SDValue DAGTypeLegalizer::WidenVecOp_UnrollVectorOp(SDNode *N) {
// The result (and first input) is legal, but the second input is illegal.
// We can't do much to fix that, so just unroll and let the extracts off of
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 16d8a9816b013..6bf67545aed4c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7146,16 +7146,14 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
case Intrinsic::scmp: {
SDValue Op1 = getValue(I.getArgOperand(0));
SDValue Op2 = getValue(I.getArgOperand(1));
- EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
- I.getType());
+ EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
setValue(&I, DAG.getNode(ISD::SCMP, sdl, DestVT, Op1, Op2));
break;
}
case Intrinsic::ucmp: {
SDValue Op1 = getValue(I.getArgOperand(0));
SDValue Op2 = getValue(I.getArgOperand(1));
- EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
- I.getType());
+ EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
setValue(&I, DAG.getNode(ISD::UCMP, sdl, DestVT, Op1, Op2));
break;
}
diff --git a/llvm/test/CodeGen/X86/scmp.ll b/llvm/test/CodeGen/X86/scmp.ll
new file mode 100644
index 0000000000000..fa951344d7934
--- /dev/null
+++ b/llvm/test/CodeGen/X86/scmp.ll
@@ -0,0 +1,794 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define i8 @scmp(i32 %x, i32 %y) {
+; CHECK-LABEL: scmp:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: setg %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovgel %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.scmp(i32 %x, i32 %y)
+ ret i8 %1
+}
+
+define i4 @scmp_narrow_result(i32 %x, i32 %y) {
+; CHECK-LABEL: scmp_narrow_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: setg %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovgel %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i4 @llvm.scmp(i32 %x, i32 %y)
+ ret i4 %1
+}
+
+define i8 @scmp_narrow_op(i62 %x, i62 %y) {
+; CHECK-LABEL: scmp_narrow_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: shlq $2, %rsi
+; CHECK-NEXT: sarq $2, %rsi
+; CHECK-NEXT: shlq $2, %rdi
+; CHECK-NEXT: sarq $2, %rdi
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: setg %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovgel %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.scmp(i62 %x, i62 %y)
+ ret i8 %1
+}
+
+define i141 @scmp_wide_result(i32 %x, i32 %y) {
+; CHECK-LABEL: scmp_wide_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: setg %cl
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovgeq %rcx, %rax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: retq
+ %1 = call i141 @llvm.scmp(i32 %x, i32 %y)
+ ret i141 %1
+}
+
+define i8 @scmp_wide_op(i109 %x, i109 %y) {
+; CHECK-LABEL: scmp_wide_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: shlq $19, %rsi
+; CHECK-NEXT: sarq $19, %rsi
+; CHECK-NEXT: shlq $19, %rcx
+; CHECK-NEXT: sarq $19, %rcx
+; CHECK-NEXT: cmpq %rdi, %rdx
+; CHECK-NEXT: movq %rcx, %rax
+; CHECK-NEXT: sbbq %rsi, %rax
+; CHECK-NEXT: setl %al
+; CHECK-NEXT: movzbl %al, %r8d
+; CHECK-NEXT: cmpq %rdx, %rdi
+; CHECK-NEXT: sbbq %rcx, %rsi
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovgel %r8d, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.scmp(i109 %x, i109 %y)
+ ret i8 %1
+}
+
+define i41 @scmp_uncommon_types(i7 %x, i7 %y) {
+; CHECK-LABEL: scmp_uncommon_types:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addb %sil, %sil
+; CHECK-NEXT: sarb %sil
+; CHECK-NEXT: addb %dil, %dil
+; CHECK-NEXT: sarb %dil
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpb %sil, %dil
+; CHECK-NEXT: setg %cl
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovgeq %rcx, %rax
+; CHECK-NEXT: retq
+ %1 = call i41 @llvm.scmp(i7 %x, i7 %y)
+ ret i41 %1
+}
+
+define <4 x i32> @scmp_normal_vectors(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: scmp_normal_vectors:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %ecx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpl %eax, %ecx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: cmovll %eax, %edx
+; CHECK-NEXT: movd %edx, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; CHECK-NEXT: movd %xmm3, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
+; CHECK-NEXT: movd %xmm3, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm3
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: movd %xmm0, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; CHECK-NEXT: movd %xmm0, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm0
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; CHECK-NEXT: movdqa %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %1 = call <4 x i32> @llvm.scmp(<4 x i32> %x, <4 x i32> %y)
+ ret <4 x i32> %1
+}
+
+define <4 x i8> @scmp_narrow_vec_result(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: scmp_narrow_vec_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %ecx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpl %eax, %ecx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: cmovll %eax, %edx
+; CHECK-NEXT: movd %edx, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; CHECK-NEXT: movd %xmm3, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
+; CHECK-NEXT: movd %xmm3, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm3
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: movd %xmm0, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; CHECK-NEXT: movd %xmm0, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm0
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; CHECK-NEXT: pxor %xmm0, %xmm0
+; CHECK-NEXT: packuswb %xmm0, %xmm2
+; CHECK-NEXT: packuswb %xmm0, %xmm2
+; CHECK-NEXT: movdqa %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %1 = call <4 x i8> @llvm.scmp(<4 x i32> %x, <4 x i32> %y)
+ ret <4 x i8> %1
+}
+
+define <4 x i32> @scmp_narrow_vec_op(<4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: scmp_narrow_vec_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
+; CHECK-NEXT: psrad $24, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
+; CHECK-NEXT: psrad $24, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,3,3,3]
+; CHECK-NEXT: movd %xmm0, %ecx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpl %eax, %ecx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: cmovll %eax, %edx
+; CHECK-NEXT: movd %edx, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; CHECK-NEXT: movd %xmm3, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,2,3]
+; CHECK-NEXT: movd %xmm3, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm3
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: movd %xmm2, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,1,1]
+; CHECK-NEXT: movd %xmm1, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm1
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
+; CHECK-NEXT: retq
+ %1 = call <4 x i32> @llvm.scmp(<4 x i8> %x, <4 x i8> %y)
+ ret <4 x i32> %1
+}
+
+define <16 x i32> @scmp_wide_vec_result(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: scmp_wide_vec_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa %xmm1, %xmm3
+; CHECK-NEXT: movdqa %xmm0, %xmm2
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm1[0],xmm5[1],xmm1[1],xmm5[2],xmm1[2],xmm5[3],xmm1[3]
+; CHECK-NEXT: psrad $24, %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm5[3,3,3,3]
+; CHECK-NEXT: movd %xmm0, %eax
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3],xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm4[0],xmm6[1],xmm4[1],xmm6[2],xmm4[2],xmm6[3],xmm4[3]
+; CHECK-NEXT: psrad $24, %xmm6
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm6[3,3,3,3]
+; CHECK-NEXT: movd %xmm0, %ecx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpl %eax, %ecx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: cmovll %eax, %edx
+; CHECK-NEXT: movd %edx, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm5[2,3,2,3]
+; CHECK-NEXT: movd %xmm7, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm6[2,3,2,3]
+; CHECK-NEXT: movd %xmm7, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm7
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm0[0],xmm7[1],xmm0[1]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: movd %xmm6, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,1,1]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,1,1]
+; CHECK-NEXT: movd %xmm5, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm5
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm7[0]
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm5 = xmm5[4],xmm1[4],xmm5[5],xmm1[5],xmm5[6],xmm1[6],xmm5[7],xmm1[7]
+; CHECK-NEXT: psrad $24, %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm5[3,3,3,3]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4,4,5,5,6,6,7,7]
+; CHECK-NEXT: psrad $24, %xmm4
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm4[3,3,3,3]
+; CHECK-NEXT: movd %xmm1, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm5[2,3,2,3]
+; CHECK-NEXT: movd %xmm6, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm4[2,3,2,3]
+; CHECK-NEXT: movd %xmm6, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm6
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm1[0],xmm6[1],xmm1[1]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: movd %xmm4, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,1,1]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,1,1]
+; CHECK-NEXT: movd %xmm4, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm4
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm6[0]
+; CHECK-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1],xmm5[2],xmm3[2],xmm5[3],xmm3[3]
+; CHECK-NEXT: psrad $24, %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm5[3,3,3,3]
+; CHECK-NEXT: movd %xmm4, %ecx
+; CHECK-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm2[8],xmm4[9],xmm2[9],xmm4[10],xmm2[10],xmm4[11],xmm2[11],xmm4[12],xmm2[12],xmm4[13],xmm2[13],xmm4[14],xmm2[14],xmm4[15],xmm2[15]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm4[0],xmm6[1],xmm4[1],xmm6[2],xmm4[2],xmm6[3],xmm4[3]
+; CHECK-NEXT: psrad $24, %xmm6
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm6[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm5[2,3,2,3]
+; CHECK-NEXT: movd %xmm7, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm6[2,3,2,3]
+; CHECK-NEXT: movd %xmm7, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm7
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm2[0],xmm7[1],xmm2[1]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: movd %xmm6, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,1,1]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,1,1]
+; CHECK-NEXT: movd %xmm5, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm5
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm7[0]
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm5 = xmm5[4],xmm3[4],xmm5[5],xmm3[5],xmm5[6],xmm3[6],xmm5[7],xmm3[7]
+; CHECK-NEXT: psrad $24, %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm5[3,3,3,3]
+; CHECK-NEXT: movd %xmm3, %ecx
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4,4,5,5,6,6,7,7]
+; CHECK-NEXT: psrad $24, %xmm4
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm4[3,3,3,3]
+; CHECK-NEXT: movd %xmm3, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm3
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm5[2,3,2,3]
+; CHECK-NEXT: movd %xmm6, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm4[2,3,2,3]
+; CHECK-NEXT: movd %xmm6, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm6
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[1]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: movd %xmm4, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm3
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,1,1]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,1,1]
+; CHECK-NEXT: movd %xmm4, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: setg %sil
+; CHECK-NEXT: cmovll %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm4
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm6[0]
+; CHECK-NEXT: retq
+ %1 = call <16 x i32> @llvm.scmp(<16 x i8> %x, <16 x i8> %y)
+ ret <16 x i32> %1
+}
+
+define <16 x i8> @scmp_wide_vec_op(<16 x i64> %x, <16 x i64> %y) {
+; CHECK-LABEL: scmp_wide_vec_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %xmm7, %rax
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: setg %cl
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovlq %rax, %rcx
+; CHECK-NEXT: movq %rcx, %xmm9
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm7[2,3,2,3]
+; CHECK-NEXT: movq %xmm7, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm7
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm7[0]
+; CHECK-NEXT: movdqa {{.*#+}} xmm7 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
+; CHECK-NEXT: pand %xmm7, %xmm9
+; CHECK-NEXT: movq %xmm6, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm8
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm6[2,3,2,3]
+; CHECK-NEXT: movq %xmm6, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm6
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm6[0]
+; CHECK-NEXT: pand %xmm7, %xmm8
+; CHECK-NEXT: packuswb %xmm9, %xmm8
+; CHECK-NEXT: movq %xmm5, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm6
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3]
+; CHECK-NEXT: movq %xmm5, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm5
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm5[0]
+; CHECK-NEXT: pand %xmm7, %xmm6
+; CHECK-NEXT: movq %xmm4, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,3,2,3]
+; CHECK-NEXT: movq %xmm4, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm4
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
+; CHECK-NEXT: pand %xmm7, %xmm5
+; CHECK-NEXT: packuswb %xmm6, %xmm5
+; CHECK-NEXT: packuswb %xmm8, %xmm5
+; CHECK-NEXT: movq %xmm3, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm4
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
+; CHECK-NEXT: movq %xmm3, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm3
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0]
+; CHECK-NEXT: pand %xmm7, %xmm4
+; CHECK-NEXT: movq %xmm2, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm3
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
+; CHECK-NEXT: movq %xmm2, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm2
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
+; CHECK-NEXT: pand %xmm7, %xmm3
+; CHECK-NEXT: packuswb %xmm4, %xmm3
+; CHECK-NEXT: movq %xmm1, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; CHECK-NEXT: movq %xmm1, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm1
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; CHECK-NEXT: pand %xmm7, %xmm2
+; CHECK-NEXT: movq %xmm0, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; CHECK-NEXT: movq %xmm0, %rcx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: setg %dl
+; CHECK-NEXT: cmovlq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %xmm0
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; CHECK-NEXT: pand %xmm7, %xmm1
+; CHECK-NEXT: packuswb %xmm2, %xmm1
+; CHECK-NEXT: packuswb %xmm3, %xmm1
+; CHECK-NEXT: packuswb %xmm5, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: retq
+ %1 = call <16 x i8> @llvm.scmp(<16 x i64> %x, <16 x i64> %y)
+ ret <16 x i8> %1
+}
+
+define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) {
+; CHECK-LABEL: scmp_uncommon_vectors:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 56
+; CHECK-NEXT: .cfi_offset %rbx, -56
+; CHECK-NEXT: .cfi_offset %r12, -48
+; CHECK-NEXT: .cfi_offset %r13, -40
+; CHECK-NEXT: .cfi_offset %r14, -32
+; CHECK-NEXT: .cfi_offset %r15, -24
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movq %rdi, %r14
+; CHECK-NEXT: movd %r8d, %xmm0
+; CHECK-NEXT: movd %ecx, %xmm1
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; CHECK-NEXT: movd %edx, %xmm2
+; CHECK-NEXT: movd %esi, %xmm0
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: movd %r9d, %xmm1
+; CHECK-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; CHECK-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT: psllw $9, %xmm0
+; CHECK-NEXT: psraw $9, %xmm0
+; CHECK-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
+; CHECK-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; CHECK-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
+; CHECK-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; CHECK-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
+; CHECK-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
+; CHECK-NEXT: psllw $9, %xmm1
+; CHECK-NEXT: psraw $9, %xmm1
+; CHECK-NEXT: movd %xmm1, %edx
+; CHECK-NEXT: movd %xmm0, %esi
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpw %dx, %si
+; CHECK-NEXT: setg %al
+; CHECK-NEXT: movl $65535, %ebp # imm = 0xFFFF
+; CHECK-NEXT: cmovll %ebp, %eax
+; CHECK-NEXT: shlq $57, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq %rax, %rcx
+; CHECK-NEXT: sarq $63, %rcx
+; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: pextrw $5, %xmm1, %esi
+; CHECK-NEXT: pextrw $5, %xmm0, %edi
+; CHECK-NEXT: xorl %r9d, %r9d
+; CHECK-NEXT: cmpw %si, %di
+; CHECK-NEXT: setg %r9b
+; CHECK-NEXT: cmovll %ebp, %r9d
+; CHECK-NEXT: shlq $57, %r9
+; CHECK-NEXT: movq %r9, %rdi
+; CHECK-NEXT: sarq $57, %rdi
+; CHECK-NEXT: sarq $63, %r9
+; CHECK-NEXT: pextrw $1, %xmm1, %esi
+; CHECK-NEXT: pextrw $1, %xmm0, %r8d
+; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: cmpw %si, %r8w
+; CHECK-NEXT: setg %bl
+; CHECK-NEXT: cmovll %ebp, %ebx
+; CHECK-NEXT: shlq $57, %rbx
+; CHECK-NEXT: movq %rbx, %rsi
+; CHECK-NEXT: sarq $57, %rsi
+; CHECK-NEXT: sarq $63, %rbx
+; CHECK-NEXT: pextrw $2, %xmm1, %r10d
+; CHECK-NEXT: pextrw $2, %xmm0, %r11d
+; CHECK-NEXT: xorl %r8d, %r8d
+; CHECK-NEXT: cmpw %r10w, %r11w
+; CHECK-NEXT: setg %r8b
+; CHECK-NEXT: cmovll %ebp, %r8d
+; CHECK-NEXT: shlq $57, %r8
+; CHECK-NEXT: movq %r8, %rdx
+; CHECK-NEXT: sarq $57, %rdx
+; CHECK-NEXT: sarq $63, %r8
+; CHECK-NEXT: pextrw $3, %xmm1, %r11d
+; CHECK-NEXT: pextrw $3, %xmm0, %r15d
+; CHECK-NEXT: xorl %r10d, %r10d
+; CHECK-NEXT: cmpw %r11w, %r15w
+; CHECK-NEXT: setg %r10b
+; CHECK-NEXT: cmovll %ebp, %r10d
+; CHECK-NEXT: shlq $57, %r10
+; CHECK-NEXT: movq %r10, %r11
+; CHECK-NEXT: sarq $57, %r11
+; CHECK-NEXT: sarq $63, %r10
+; CHECK-NEXT: pextrw $4, %xmm1, %r12d
+; CHECK-NEXT: pextrw $4, %xmm0, %r13d
+; CHECK-NEXT: xorl %r15d, %r15d
+; CHECK-NEXT: cmpw %r12w, %r13w
+; CHECK-NEXT: setg %r15b
+; CHECK-NEXT: cmovll %ebp, %r15d
+; CHECK-NEXT: shlq $57, %r15
+; CHECK-NEXT: movq %r15, %r12
+; CHECK-NEXT: sarq $57, %r12
+; CHECK-NEXT: sarq $63, %r15
+; CHECK-NEXT: pextrw $6, %xmm1, %ecx
+; CHECK-NEXT: pextrw $6, %xmm0, %eax
+; CHECK-NEXT: xorl %r13d, %r13d
+; CHECK-NEXT: cmpw %cx, %ax
+; CHECK-NEXT: setg %r13b
+; CHECK-NEXT: cmovll %ebp, %r13d
+; CHECK-NEXT: shlq $57, %r13
+; CHECK-NEXT: movq %r13, %rbp
+; CHECK-NEXT: sarq $57, %rbp
+; CHECK-NEXT: sarq $63, %r13
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: sarq $57, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq %rax, (%r14)
+; CHECK-NEXT: movq %r13, %rax
+; CHECK-NEXT: shldq $62, %rbp, %rax
+; CHECK-NEXT: movq %rax, 88(%r14)
+; CHECK-NEXT: movq %r15, %rax
+; CHECK-NEXT: shldq $20, %r12, %rax
+; CHECK-NEXT: movq %rax, 64(%r14)
+; CHECK-NEXT: movq %r10, %rax
+; CHECK-NEXT: shldq $31, %r11, %rax
+; CHECK-NEXT: movq %rax, 48(%r14)
+; CHECK-NEXT: movq %r8, %rax
+; CHECK-NEXT: shldq $42, %rdx, %rax
+; CHECK-NEXT: movq %rax, 32(%r14)
+; CHECK-NEXT: movabsq $9007199254738944, %rax # imm = 0x1FFFFFFFFFF800
+; CHECK-NEXT: andq %rbx, %rax
+; CHECK-NEXT: shldq $53, %rsi, %rbx
+; CHECK-NEXT: movq %rbx, 16(%r14)
+; CHECK-NEXT: movq %r13, %rcx
+; CHECK-NEXT: shrq $34, %rcx
+; CHECK-NEXT: movw %cx, 100(%r14)
+; CHECK-NEXT: movabsq $9007199254740991, %rbx # imm = 0x1FFFFFFFFFFFFF
+; CHECK-NEXT: andq %rbx, %r9
+; CHECK-NEXT: shldq $9, %rdi, %r9
+; CHECK-NEXT: shlq $62, %rbp
+; CHECK-NEXT: orq %r9, %rbp
+; CHECK-NEXT: shrq $2, %r13
+; CHECK-NEXT: movl %r13d, 96(%r14)
+; CHECK-NEXT: movq %rbp, 80(%r14)
+; CHECK-NEXT: shlq $42, %rdx
+; CHECK-NEXT: shrq $11, %rax
+; CHECK-NEXT: orq %rdx, %rax
+; CHECK-NEXT: movq %rax, 24(%r14)
+; CHECK-NEXT: movabsq $2251799813685247, %rax # imm = 0x7FFFFFFFFFFFF
+; CHECK-NEXT: andq %r13, %rax
+; CHECK-NEXT: shrq $48, %rax
+; CHECK-NEXT: movb %al, 102(%r14)
+; CHECK-NEXT: shlq $9, %rdi
+; CHECK-NEXT: shrq $44, %r15
+; CHECK-NEXT: andl $511, %r15d # imm = 0x1FF
+; CHECK-NEXT: orq %rdi, %r15
+; CHECK-NEXT: movq %r15, 72(%r14)
+; CHECK-NEXT: shlq $20, %r12
+; CHECK-NEXT: shrq $33, %r10
+; CHECK-NEXT: andl $1048575, %r10d # imm = 0xFFFFF
+; CHECK-NEXT: orq %r12, %r10
+; CHECK-NEXT: movq %r10, 56(%r14)
+; CHECK-NEXT: shlq $31, %r11
+; CHECK-NEXT: shrq $22, %r8
+; CHECK-NEXT: andl $2147483647, %r8d # imm = 0x7FFFFFFF
+; CHECK-NEXT: orq %r11, %r8
+; CHECK-NEXT: movq %r8, 40(%r14)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Folded Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; CHECK-NEXT: movq %xmm0, %rax
+; CHECK-NEXT: andq %rbx, %rax
+; CHECK-NEXT: shlq $53, %rsi
+; CHECK-NEXT: orq %rax, %rsi
+; CHECK-NEXT: movq %rsi, 8(%r14)
+; CHECK-NEXT: movq %r14, %rax
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
+ %1 = call <7 x i117> @llvm.scmp(<7 x i7> %x, <7 x i7> %y)
+ ret <7 x i117> %1
+}
+
+define <1 x i3> @scmp_scalarize(<1 x i33> %x, <1 x i33> %y) {
+; CHECK-LABEL: scmp_scalarize:
+; CHECK: # %bb.0:
+; CHECK-NEXT: shlq $31, %rsi
+; CHECK-NEXT: sarq $31, %rsi
+; CHECK-NEXT: shlq $31, %rdi
+; CHECK-NEXT: sarq $31, %rdi
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: setg %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovgel %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call <1 x i3> @llvm.scmp(<1 x i33> %x, <1 x i33> %y)
+ ret <1 x i3> %1
+}
diff --git a/llvm/test/CodeGen/X86/ucmp.ll b/llvm/test/CodeGen/X86/ucmp.ll
new file mode 100644
index 0000000000000..663df32e728a4
--- /dev/null
+++ b/llvm/test/CodeGen/X86/ucmp.ll
@@ -0,0 +1,1010 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define i8 @ucmp(i32 %x, i32 %y) {
+; CHECK-LABEL: ucmp:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
+ ret i8 %1
+}
+
+define i4 @ucmp_narrow_result(i32 %x, i32 %y) {
+; CHECK-LABEL: ucmp_narrow_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i4 @llvm.ucmp(i32 %x, i32 %y)
+ ret i4 %1
+}
+
+define i8 @ucmp_narrow_op(i62 %x, i62 %y) {
+; CHECK-LABEL: ucmp_narrow_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movabsq $4611686018427387903, %rax # imm = 0x3FFFFFFFFFFFFFFF
+; CHECK-NEXT: andq %rax, %rsi
+; CHECK-NEXT: andq %rax, %rdi
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.ucmp(i62 %x, i62 %y)
+ ret i8 %1
+}
+
+define i141 @ucmp_wide_result(i32 %x, i32 %y) {
+; CHECK-LABEL: ucmp_wide_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaeq %rcx, %rax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: retq
+ %1 = call i141 @llvm.ucmp(i32 %x, i32 %y)
+ ret i141 %1
+}
+
+define i8 @ucmp_wide_op(i109 %x, i109 %y) {
+; CHECK-LABEL: ucmp_wide_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movabsq $35184372088831, %rax # imm = 0x1FFFFFFFFFFF
+; CHECK-NEXT: andq %rax, %rsi
+; CHECK-NEXT: andq %rax, %rcx
+; CHECK-NEXT: cmpq %rdi, %rdx
+; CHECK-NEXT: movq %rcx, %rax
+; CHECK-NEXT: sbbq %rsi, %rax
+; CHECK-NEXT: setb %al
+; CHECK-NEXT: movzbl %al, %r8d
+; CHECK-NEXT: cmpq %rdx, %rdi
+; CHECK-NEXT: sbbq %rcx, %rsi
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %r8d, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.ucmp(i109 %x, i109 %y)
+ ret i8 %1
+}
+
+define i41 @ucmp_uncommon_types(i7 %x, i7 %y) {
+; CHECK-LABEL: ucmp_uncommon_types:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andb $127, %sil
+; CHECK-NEXT: andb $127, %dil
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpb %sil, %dil
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaeq %rcx, %rax
+; CHECK-NEXT: retq
+ %1 = call i41 @llvm.ucmp(i7 %x, i7 %y)
+ ret i41 %1
+}
+
+define <4 x i32> @ucmp_normal_vectors(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: ucmp_normal_vectors:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %ecx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpl %eax, %ecx
+; CHECK-NEXT: seta %dl
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: movd %edx, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; CHECK-NEXT: movd %xmm3, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
+; CHECK-NEXT: movd %xmm3, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm3
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: movd %xmm0, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; CHECK-NEXT: movd %xmm0, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm0
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; CHECK-NEXT: movdqa %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %1 = call <4 x i32> @llvm.ucmp(<4 x i32> %x, <4 x i32> %y)
+ ret <4 x i32> %1
+}
+
+define <4 x i8> @ucmp_narrow_vec_result(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: ucmp_narrow_vec_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %ecx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpl %eax, %ecx
+; CHECK-NEXT: seta %dl
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: movd %edx, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; CHECK-NEXT: movd %xmm3, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
+; CHECK-NEXT: movd %xmm3, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm3
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: movd %xmm0, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; CHECK-NEXT: movd %xmm0, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm0
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; CHECK-NEXT: pxor %xmm0, %xmm0
+; CHECK-NEXT: packuswb %xmm0, %xmm2
+; CHECK-NEXT: packuswb %xmm0, %xmm2
+; CHECK-NEXT: movdqa %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %1 = call <4 x i8> @llvm.ucmp(<4 x i32> %x, <4 x i32> %y)
+ ret <4 x i8> %1
+}
+
+define <4 x i32> @ucmp_narrow_vec_op(<4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: ucmp_narrow_vec_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pxor %xmm2, %xmm2
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; CHECK-NEXT: pextrw $0, %xmm1, %ecx
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[3,3,3,3]
+; CHECK-NEXT: movd %xmm3, %eax
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; CHECK-NEXT: pextrw $0, %xmm0, %edx
+; CHECK-NEXT: movdqa %xmm0, %xmm3
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,3,3,3]
+; CHECK-NEXT: movd %xmm0, %esi
+; CHECK-NEXT: xorl %edi, %edi
+; CHECK-NEXT: cmpl %eax, %esi
+; CHECK-NEXT: seta %dil
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: cmovbl %eax, %edi
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; CHECK-NEXT: movd %xmm0, %esi
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,2,3]
+; CHECK-NEXT: movd %xmm0, %r8d
+; CHECK-NEXT: xorl %r9d, %r9d
+; CHECK-NEXT: cmpl %esi, %r8d
+; CHECK-NEXT: movd %edi, %xmm0
+; CHECK-NEXT: seta %r9b
+; CHECK-NEXT: cmovbl %eax, %r9d
+; CHECK-NEXT: movd %r9d, %xmm2
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,1,1]
+; CHECK-NEXT: movd %xmm1, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm1
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT: retq
+ %1 = call <4 x i32> @llvm.ucmp(<4 x i8> %x, <4 x i8> %y)
+ ret <4 x i32> %1
+}
+
+define <16 x i32> @ucmp_wide_vec_result(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: ucmp_wide_vec_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 56
+; CHECK-NEXT: .cfi_offset %rbx, -56
+; CHECK-NEXT: .cfi_offset %r12, -48
+; CHECK-NEXT: .cfi_offset %r13, -40
+; CHECK-NEXT: .cfi_offset %r14, -32
+; CHECK-NEXT: .cfi_offset %r15, -24
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: pxor %xmm2, %xmm2
+; CHECK-NEXT: movdqa %xmm1, %xmm4
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3],xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
+; CHECK-NEXT: pextrw $0, %xmm4, %edi
+; CHECK-NEXT: movdqa %xmm4, %xmm3
+; CHECK-NEXT: pextrw $4, %xmm4, %r11d
+; CHECK-NEXT: movdqa %xmm4, %xmm5
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1],xmm5[2],xmm2[2],xmm5[3],xmm2[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm5[3,3,3,3]
+; CHECK-NEXT: movd %xmm4, %eax
+; CHECK-NEXT: movdqa %xmm0, %xmm6
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[1],xmm6[2],xmm2[2],xmm6[3],xmm2[3],xmm6[4],xmm2[4],xmm6[5],xmm2[5],xmm6[6],xmm2[6],xmm6[7],xmm2[7]
+; CHECK-NEXT: pextrw $0, %xmm6, %r8d
+; CHECK-NEXT: movdqa %xmm6, %xmm4
+; CHECK-NEXT: pextrw $4, %xmm6, %ebx
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[1],xmm6[2],xmm2[2],xmm6[3],xmm2[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm6[3,3,3,3]
+; CHECK-NEXT: movd %xmm7, %ecx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %eax, %ecx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: movl $-1, %edx
+; CHECK-NEXT: cmovbl %edx, %esi
+; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm5[2,3,2,3]
+; CHECK-NEXT: movd %xmm7, %esi
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm6[2,3,2,3]
+; CHECK-NEXT: movd %xmm7, %r9d
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpl %esi, %r9d
+; CHECK-NEXT: seta %al
+; CHECK-NEXT: cmovbl %edx, %eax
+; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %edi, %r8d
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %edx, %esi
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,1,1]
+; CHECK-NEXT: movd %xmm5, %r8d
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,1,1]
+; CHECK-NEXT: movd %xmm5, %r9d
+; CHECK-NEXT: xorl %edi, %edi
+; CHECK-NEXT: cmpl %r8d, %r9d
+; CHECK-NEXT: seta %dil
+; CHECK-NEXT: cmovbl %edx, %edi
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm3[3,3,3,3]
+; CHECK-NEXT: movd %xmm5, %r9d
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[3,3,3,3]
+; CHECK-NEXT: movd %xmm5, %r10d
+; CHECK-NEXT: xorl %r8d, %r8d
+; CHECK-NEXT: cmpl %r9d, %r10d
+; CHECK-NEXT: seta %r8b
+; CHECK-NEXT: cmovbl %edx, %r8d
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm3[2,3,2,3]
+; CHECK-NEXT: movd %xmm5, %r10d
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; CHECK-NEXT: movd %xmm5, %ebp
+; CHECK-NEXT: xorl %r9d, %r9d
+; CHECK-NEXT: cmpl %r10d, %ebp
+; CHECK-NEXT: seta %r9b
+; CHECK-NEXT: cmovbl %edx, %r9d
+; CHECK-NEXT: xorl %r10d, %r10d
+; CHECK-NEXT: cmpl %r11d, %ebx
+; CHECK-NEXT: seta %r10b
+; CHECK-NEXT: cmovbl %edx, %r10d
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,1,1]
+; CHECK-NEXT: movd %xmm3, %ebx
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,1,1]
+; CHECK-NEXT: movd %xmm3, %ebp
+; CHECK-NEXT: xorl %r11d, %r11d
+; CHECK-NEXT: cmpl %ebx, %ebp
+; CHECK-NEXT: seta %r11b
+; CHECK-NEXT: cmovbl %edx, %r11d
+; CHECK-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm2[8],xmm1[9],xmm2[9],xmm1[10],xmm2[10],xmm1[11],xmm2[11],xmm1[12],xmm2[12],xmm1[13],xmm2[13],xmm1[14],xmm2[14],xmm1[15],xmm2[15]
+; CHECK-NEXT: pextrw $0, %xmm1, %r15d
+; CHECK-NEXT: movdqa %xmm1, %xmm4
+; CHECK-NEXT: movdqa %xmm1, %xmm3
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm3[3,3,3,3]
+; CHECK-NEXT: movd %xmm5, %ebp
+; CHECK-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm2[8],xmm0[9],xmm2[9],xmm0[10],xmm2[10],xmm0[11],xmm2[11],xmm0[12],xmm2[12],xmm0[13],xmm2[13],xmm0[14],xmm2[14],xmm0[15],xmm2[15]
+; CHECK-NEXT: pextrw $0, %xmm0, %r12d
+; CHECK-NEXT: movdqa %xmm0, %xmm5
+; CHECK-NEXT: movdqa %xmm0, %xmm6
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[1],xmm6[2],xmm2[2],xmm6[3],xmm2[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm6[3,3,3,3]
+; CHECK-NEXT: movd %xmm7, %r14d
+; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: cmpl %ebp, %r14d
+; CHECK-NEXT: seta %bl
+; CHECK-NEXT: cmovbl %edx, %ebx
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm3[2,3,2,3]
+; CHECK-NEXT: movd %xmm7, %r14d
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm6[2,3,2,3]
+; CHECK-NEXT: movd %xmm7, %r13d
+; CHECK-NEXT: xorl %ebp, %ebp
+; CHECK-NEXT: cmpl %r14d, %r13d
+; CHECK-NEXT: seta %bpl
+; CHECK-NEXT: cmovbl %edx, %ebp
+; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: cmpl %r15d, %r12d
+; CHECK-NEXT: seta %r14b
+; CHECK-NEXT: cmovbl %edx, %r14d
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,1,1]
+; CHECK-NEXT: movd %xmm3, %r12d
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,1,1]
+; CHECK-NEXT: movd %xmm3, %r13d
+; CHECK-NEXT: xorl %r15d, %r15d
+; CHECK-NEXT: cmpl %r12d, %r13d
+; CHECK-NEXT: seta %r15b
+; CHECK-NEXT: cmovbl %edx, %r15d
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm4[3,3,3,3]
+; CHECK-NEXT: movd %xmm3, %r13d
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm5 = xmm5[4],xmm2[4],xmm5[5],xmm2[5],xmm5[6],xmm2[6],xmm5[7],xmm2[7]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm5[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: xorl %r12d, %r12d
+; CHECK-NEXT: cmpl %r13d, %eax
+; CHECK-NEXT: seta %r12b
+; CHECK-NEXT: cmovbl %edx, %r12d
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm4[2,3,2,3]
+; CHECK-NEXT: movd %xmm2, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm5[2,3,2,3]
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: xorl %r13d, %r13d
+; CHECK-NEXT: cmpl %ecx, %eax
+; CHECK-NEXT: movd {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 4-byte Folded Reload
+; CHECK-NEXT: # xmm2 = mem[0],zero,zero,zero
+; CHECK-NEXT: pextrw $4, %xmm1, %eax
+; CHECK-NEXT: movd {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 4-byte Folded Reload
+; CHECK-NEXT: # xmm3 = mem[0],zero,zero,zero
+; CHECK-NEXT: pextrw $4, %xmm0, %ecx
+; CHECK-NEXT: movd %esi, %xmm0
+; CHECK-NEXT: movd %edi, %xmm6
+; CHECK-NEXT: movd %r8d, %xmm7
+; CHECK-NEXT: movd %r9d, %xmm8
+; CHECK-NEXT: movd %r10d, %xmm1
+; CHECK-NEXT: movd %r11d, %xmm9
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT: movd %ebx, %xmm10
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[1]
+; CHECK-NEXT: movd %ebp, %xmm6
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
+; CHECK-NEXT: movd %r14d, %xmm2
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1]
+; CHECK-NEXT: movd %r15d, %xmm3
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm9[0],xmm1[1],xmm9[1]
+; CHECK-NEXT: movd %r12d, %xmm7
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm8[0]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm10[0],xmm6[1],xmm10[1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0]
+; CHECK-NEXT: seta %r13b
+; CHECK-NEXT: cmovbl %edx, %r13d
+; CHECK-NEXT: movd %r13d, %xmm6
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %eax, %ecx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %edx, %esi
+; CHECK-NEXT: movd %esi, %xmm3
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,1,1]
+; CHECK-NEXT: movd %xmm4, %eax
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,1,1]
+; CHECK-NEXT: movd %xmm4, %ecx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %eax, %ecx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %edx, %esi
+; CHECK-NEXT: movd %esi, %xmm4
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm6[0]
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
+ %1 = call <16 x i32> @llvm.ucmp(<16 x i8> %x, <16 x i8> %y)
+ ret <16 x i32> %1
+}
+
+define <16 x i8> @ucmp_wide_vec_op(<16 x i32> %x, <16 x i32> %y) {
+; CHECK-LABEL: ucmp_wide_vec_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm7[3,3,3,3]
+; CHECK-NEXT: movd %xmm8, %eax
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm3[3,3,3,3]
+; CHECK-NEXT: movd %xmm8, %ecx
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpl %eax, %ecx
+; CHECK-NEXT: seta %dl
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: movd %edx, %xmm8
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm7[2,3,2,3]
+; CHECK-NEXT: movd %xmm9, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm3[2,3,2,3]
+; CHECK-NEXT: movd %xmm9, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm9
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm8[0],xmm9[1],xmm8[1]
+; CHECK-NEXT: movd %xmm7, %ecx
+; CHECK-NEXT: movd %xmm3, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm8
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm7[1,1,1,1]
+; CHECK-NEXT: movd %xmm7, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,1,1]
+; CHECK-NEXT: movd %xmm3, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm3
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm3[0],xmm8[1],xmm3[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm9[0]
+; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
+; CHECK-NEXT: pand %xmm3, %xmm8
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm6[3,3,3,3]
+; CHECK-NEXT: movd %xmm7, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm2[3,3,3,3]
+; CHECK-NEXT: movd %xmm7, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm7
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm6[2,3,2,3]
+; CHECK-NEXT: movd %xmm9, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm2[2,3,2,3]
+; CHECK-NEXT: movd %xmm9, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm9
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm7[0],xmm9[1],xmm7[1]
+; CHECK-NEXT: movd %xmm6, %ecx
+; CHECK-NEXT: movd %xmm2, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm7
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,1,1]
+; CHECK-NEXT: movd %xmm6, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,1,1]
+; CHECK-NEXT: movd %xmm2, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm2
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm2[0],xmm7[1],xmm2[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm9[0]
+; CHECK-NEXT: pand %xmm3, %xmm7
+; CHECK-NEXT: packuswb %xmm8, %xmm7
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm5[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
+; CHECK-NEXT: movd %xmm2, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm5[2,3,2,3]
+; CHECK-NEXT: movd %xmm6, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm1[2,3,2,3]
+; CHECK-NEXT: movd %xmm6, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm6
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[1]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: movd %xmm1, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,1,1]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; CHECK-NEXT: movd %xmm1, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm1
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0]
+; CHECK-NEXT: pand %xmm3, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm4[3,3,3,3]
+; CHECK-NEXT: movd %xmm1, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,3,3,3]
+; CHECK-NEXT: movd %xmm1, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; CHECK-NEXT: movd %xmm5, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm0[2,3,2,3]
+; CHECK-NEXT: movd %xmm5, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm5
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm1[0],xmm5[1],xmm1[1]
+; CHECK-NEXT: movd %xmm4, %ecx
+; CHECK-NEXT: movd %xmm0, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,1,1]
+; CHECK-NEXT: movd %xmm4, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; CHECK-NEXT: movd %xmm0, %edx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: cmpl %ecx, %edx
+; CHECK-NEXT: seta %sil
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: movd %esi, %xmm0
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm5[0]
+; CHECK-NEXT: pand %xmm3, %xmm1
+; CHECK-NEXT: packuswb %xmm2, %xmm1
+; CHECK-NEXT: packuswb %xmm7, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: retq
+ %1 = call <16 x i8> @llvm.ucmp(<16 x i32> %x, <16 x i32> %y)
+ ret <16 x i8> %1
+}
+
+define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) {
+; CHECK-LABEL: ucmp_uncommon_vectors:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 56
+; CHECK-NEXT: subq $72, %rsp
+; CHECK-NEXT: .cfi_def_cfa_offset 128
+; CHECK-NEXT: .cfi_offset %rbx, -56
+; CHECK-NEXT: .cfi_offset %r12, -48
+; CHECK-NEXT: .cfi_offset %r13, -40
+; CHECK-NEXT: .cfi_offset %r14, -32
+; CHECK-NEXT: .cfi_offset %r15, -24
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq %rdx, %xmm0
+; CHECK-NEXT: movq %rsi, %xmm1
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; CHECK-NEXT: movq %xmm0, %rax
+; CHECK-NEXT: andl $127, %eax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: andl $127, %edx
+; CHECK-NEXT: cmpq %rsi, %r10
+; CHECK-NEXT: movq %rdx, %rdi
+; CHECK-NEXT: sbbq %rax, %rdi
+; CHECK-NEXT: setb %dil
+; CHECK-NEXT: movzbl %dil, %edi
+; CHECK-NEXT: cmpq %r10, %rsi
+; CHECK-NEXT: sbbq %rdx, %rax
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovbq %rax, %rdi
+; CHECK-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: andl $127, %edx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rsi
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; CHECK-NEXT: andl $127, %edi
+; CHECK-NEXT: cmpq %r11, %rsi
+; CHECK-NEXT: movq %rdi, %r10
+; CHECK-NEXT: sbbq %rdx, %r10
+; CHECK-NEXT: setb %r10b
+; CHECK-NEXT: movzbl %r10b, %r10d
+; CHECK-NEXT: cmpq %rsi, %r11
+; CHECK-NEXT: sbbq %rdi, %rdx
+; CHECK-NEXT: cmovbq %rax, %r10
+; CHECK-NEXT: movq %r10, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq %r9, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq %r9, %xmm0
+; CHECK-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; CHECK-NEXT: movq %xmm0, %rdx
+; CHECK-NEXT: andl $127, %edx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rsi
+; CHECK-NEXT: andl $127, %esi
+; CHECK-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmpq %r9, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: sbbq %rdx, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq %r8, %xmm0
+; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq %rcx, %xmm1
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; CHECK-NEXT: movq %xmm0, %r15
+; CHECK-NEXT: andl $127, %r15d
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r12
+; CHECK-NEXT: andl $127, %r12d
+; CHECK-NEXT: cmpq %rcx, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r12, %rax
+; CHECK-NEXT: sbbq %r15, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: andl $127, %eax
+; CHECK-NEXT: movq %rax, %rdx
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rsi
+; CHECK-NEXT: andl $127, %esi
+; CHECK-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmpq %rcx, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: sbbq %rdx, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: andl $127, %eax
+; CHECK-NEXT: movq %rax, %rcx
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: andl $127, %edx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: sbbq %rcx, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: andl $127, %eax
+; CHECK-NEXT: movq %rax, %rcx
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: andl $127, %edx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: sbbq %rcx, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: andl $127, %eax
+; CHECK-NEXT: movq %rax, %rcx
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: andl $127, %edx
+; CHECK-NEXT: movq %rdx, (%rsp) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: sbbq %rcx, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: andl $127, %eax
+; CHECK-NEXT: movq %rax, %rcx
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: andl $127, %edx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: sbbq %rcx, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: andl $127, %eax
+; CHECK-NEXT: movq %rax, %rcx
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: andl $127, %edx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: sbbq %rcx, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: andl $127, %eax
+; CHECK-NEXT: movq %rax, %rcx
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: andl $127, %edx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: sbbq %rcx, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: andl $127, %eax
+; CHECK-NEXT: movq %rax, %rcx
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: andl $127, %edx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: sbbq %rcx, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r13
+; CHECK-NEXT: andl $127, %r13d
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rbp
+; CHECK-NEXT: andl $127, %ebp
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rbp, %rax
+; CHECK-NEXT: sbbq %r13, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; CHECK-NEXT: andl $127, %ebx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r14
+; CHECK-NEXT: andl $127, %r14d
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r14, %rax
+; CHECK-NEXT: sbbq %rbx, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r9
+; CHECK-NEXT: andl $127, %r9d
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: andl $127, %r11d
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r11, %rax
+; CHECK-NEXT: sbbq %r9, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; CHECK-NEXT: andl $127, %edi
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r8
+; CHECK-NEXT: andl $127, %r8d
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r8, %rax
+; CHECK-NEXT: sbbq %rdi, %rax
+; CHECK-NEXT: setb {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Folded Spill
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: andl $127, %ecx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: andl $127, %edx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rdx, %r10
+; CHECK-NEXT: sbbq %rcx, %r10
+; CHECK-NEXT: setb %r10b
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
+; CHECK-NEXT: andl $3, %esi
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: sbbq %r12, %r15
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 1-byte Folded Reload
+; CHECK-NEXT: movl $-1, %r15d
+; CHECK-NEXT: cmovbl %r15d, %eax
+; CHECK-NEXT: andl $3, %eax
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Reload
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %r12
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Reload
+; CHECK-NEXT: sbbq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload
+; CHECK-NEXT: leaq (%rsi,%rax,4), %rsi
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %eax
+; CHECK-NEXT: andl $3, %eax
+; CHECK-NEXT: shll $4, %eax
+; CHECK-NEXT: orq %rsi, %rax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rsi
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rsi
+; CHECK-NEXT: sbbq %rdx, %rcx
+; CHECK-NEXT: movzbl %r10b, %ecx
+; CHECK-NEXT: cmovbl %r15d, %ecx
+; CHECK-NEXT: andl $3, %ecx
+; CHECK-NEXT: shll $6, %ecx
+; CHECK-NEXT: orq %rax, %rcx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: sbbq %r8, %rdi
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %r12d # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %r12d
+; CHECK-NEXT: andl $3, %r12d
+; CHECK-NEXT: shll $8, %r12d
+; CHECK-NEXT: orq %rcx, %r12
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: sbbq %r11, %r9
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %eax
+; CHECK-NEXT: andl $3, %eax
+; CHECK-NEXT: shll $10, %eax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: sbbq %r14, %rbx
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %ecx
+; CHECK-NEXT: andl $3, %ecx
+; CHECK-NEXT: shll $12, %ecx
+; CHECK-NEXT: orq %rax, %rcx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: sbbq %rbp, %r13
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %eax
+; CHECK-NEXT: andl $3, %eax
+; CHECK-NEXT: shll $14, %eax
+; CHECK-NEXT: orq %rcx, %rax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
+; CHECK-NEXT: sbbq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Folded Reload
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %ecx
+; CHECK-NEXT: andl $3, %ecx
+; CHECK-NEXT: shll $16, %ecx
+; CHECK-NEXT: orq %rax, %rcx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: sbbq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Folded Reload
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %eax
+; CHECK-NEXT: andl $3, %eax
+; CHECK-NEXT: shll $18, %eax
+; CHECK-NEXT: orq %rcx, %rax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
+; CHECK-NEXT: sbbq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Folded Reload
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %ecx
+; CHECK-NEXT: andl $3, %ecx
+; CHECK-NEXT: shll $20, %ecx
+; CHECK-NEXT: orq %rax, %rcx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: sbbq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Folded Reload
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %eax
+; CHECK-NEXT: andl $3, %eax
+; CHECK-NEXT: shll $22, %eax
+; CHECK-NEXT: orq %rcx, %rax
+; CHECK-NEXT: orq %r12, %rax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
+; CHECK-NEXT: sbbq (%rsp), %rcx # 8-byte Folded Reload
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %ecx
+; CHECK-NEXT: andl $3, %ecx
+; CHECK-NEXT: shll $24, %ecx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
+; CHECK-NEXT: sbbq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Folded Reload
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %edx
+; CHECK-NEXT: andl $3, %edx
+; CHECK-NEXT: shlq $26, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
+; CHECK-NEXT: sbbq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Folded Reload
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %ecx
+; CHECK-NEXT: andl $3, %ecx
+; CHECK-NEXT: shlq $28, %rcx
+; CHECK-NEXT: orq %rdx, %rcx
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
+; CHECK-NEXT: andl $3, %edx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rsi
+; CHECK-NEXT: cmpq {{[0-9]+}}(%rsp), %rsi
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
+; CHECK-NEXT: sbbq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Folded Reload
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
+; CHECK-NEXT: movb %dl, 4(%rsi)
+; CHECK-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 1-byte Folded Reload
+; CHECK-NEXT: cmovbl %r15d, %edx
+; CHECK-NEXT: andl $3, %edx
+; CHECK-NEXT: shlq $30, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: orq %rax, %rdx
+; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: movl %edx, (%rsi)
+; CHECK-NEXT: addq $72, %rsp
+; CHECK-NEXT: .cfi_def_cfa_offset 56
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
+ %1 = call <17 x i2> @llvm.ucmp(<17 x i71> %x, <17 x i71> %y)
+ ret <17 x i2> %1
+}
diff --git a/llvm/test/CodeGen/X86/uscmp.ll b/llvm/test/CodeGen/X86/uscmp.ll
deleted file mode 100644
index 3d1765b94f72a..0000000000000
--- a/llvm/test/CodeGen/X86/uscmp.ll
+++ /dev/null
@@ -1,129 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
-
-define i8 @ucmp(i32 %x, i32 %y) {
-; CHECK-LABEL: ucmp:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: cmpl %esi, %edi
-; CHECK-NEXT: seta %cl
-; CHECK-NEXT: movl $255, %eax
-; CHECK-NEXT: cmovael %ecx, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: retq
- %1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
- ret i8 %1
-}
-
-define i8 @scmp(i32 %x, i32 %y) {
-; CHECK-LABEL: scmp:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: cmpl %esi, %edi
-; CHECK-NEXT: seta %cl
-; CHECK-NEXT: movl $255, %eax
-; CHECK-NEXT: cmovael %ecx, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: retq
- %1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
- ret i8 %1
-}
-
-define i4 @ucmp_narrow_result(i32 %x, i32 %y) {
-; CHECK-LABEL: ucmp_narrow_result:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: cmpl %esi, %edi
-; CHECK-NEXT: seta %cl
-; CHECK-NEXT: movl $255, %eax
-; CHECK-NEXT: cmovael %ecx, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: retq
- %1 = call i4 @llvm.ucmp(i32 %x, i32 %y)
- ret i4 %1
-}
-
-define i8 @scmp_narrow_op(i5 %x, i5 %y) {
-; CHECK-LABEL: scmp_narrow_op:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andb $31, %sil
-; CHECK-NEXT: andb $31, %dil
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: cmpb %sil, %dil
-; CHECK-NEXT: seta %cl
-; CHECK-NEXT: movl $255, %eax
-; CHECK-NEXT: cmovael %ecx, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: retq
- %1 = call i8 @llvm.ucmp(i5 %x, i5 %y)
- ret i8 %1
-}
-
-define i128 @ucmp_wide_result(i32 %x, i32 %y) {
-; CHECK-LABEL: ucmp_wide_result:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: cmpl %esi, %edi
-; CHECK-NEXT: seta %cl
-; CHECK-NEXT: movq $-1, %rax
-; CHECK-NEXT: cmovaeq %rcx, %rax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: retq
- %1 = call i128 @llvm.ucmp(i32 %x, i32 %y)
- ret i128 %1
-}
-
-define i8 @scmp_wide_op(i128 %x, i128 %y) {
-; CHECK-LABEL: scmp_wide_op:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpq %rdi, %rdx
-; CHECK-NEXT: movq %rcx, %rax
-; CHECK-NEXT: sbbq %rsi, %rax
-; CHECK-NEXT: setl %al
-; CHECK-NEXT: movzbl %al, %r8d
-; CHECK-NEXT: cmpq %rdx, %rdi
-; CHECK-NEXT: sbbq %rcx, %rsi
-; CHECK-NEXT: movl $255, %eax
-; CHECK-NEXT: cmovgel %r8d, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: retq
- %1 = call i8 @llvm.scmp(i128 %x, i128 %y)
- ret i8 %1
-}
-
-define i41 @ucmp_uncommon_types(i7 %x, i7 %y) {
-; CHECK-LABEL: ucmp_uncommon_types:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andb $127, %sil
-; CHECK-NEXT: andb $127, %dil
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: cmpb %sil, %dil
-; CHECK-NEXT: seta %cl
-; CHECK-NEXT: movq $-1, %rax
-; CHECK-NEXT: cmovaeq %rcx, %rax
-; CHECK-NEXT: retq
- %1 = call i41 @llvm.ucmp(i7 %x, i7 %y)
- ret i41 %1
-}
-
-define i125 @scmp_uncommon_types(i99 %x, i99 %y) {
-; CHECK-LABEL: scmp_uncommon_types:
-; CHECK: # %bb.0:
-; CHECK-NEXT: shlq $29, %rsi
-; CHECK-NEXT: sarq $29, %rsi
-; CHECK-NEXT: shlq $29, %rcx
-; CHECK-NEXT: sarq $29, %rcx
-; CHECK-NEXT: cmpq %rdi, %rdx
-; CHECK-NEXT: movq %rcx, %rax
-; CHECK-NEXT: sbbq %rsi, %rax
-; CHECK-NEXT: setl %al
-; CHECK-NEXT: movzbl %al, %r8d
-; CHECK-NEXT: cmpq %rdx, %rdi
-; CHECK-NEXT: sbbq %rcx, %rsi
-; CHECK-NEXT: movq $-1, %rax
-; CHECK-NEXT: cmovgeq %r8, %rax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: retq
- %1 = call i125 @llvm.scmp(i99 %x, i99 %y)
- ret i125 %1
-}
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