[llvm] [LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (PR #92799)

[Philip Reames via llvm-commits]

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@@ -10,10 +10,9 @@ define <8 x i7> @vdivu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
 ; CHECK-LABEL: vdivu_vv_v8i7:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 127
-; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT:    vand.vx v9, v9, a1
-; CHECK-NEXT:    vand.vx v8, v8, a1
 ; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT:    vand.vx v9, v9, a1, v0.t
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preames wrote:

On the correctness concern, I'd gotten myself confused by assuming that the vp.udiv must have a passthru and skimming the assembly with that mindset.  

I'm fine with masking in this change.  If anyone cares about performance of vp code, we should probably be doing a generic combine to strip masking when it doesn't mater.

https://github.com/llvm/llvm-project/pull/92799