[llvm] [BOLT][AArch64] Implement PLTCall optimization (PR #93584)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 3bde7983986d8ce637f6bb506860859249787751 f8681fdcc445ca12c8d53b3c799687ecf5015909 -- bolt/test/Inputs/plt-tailcall.c bolt/include/bolt/Core/MCPlusBuilder.h bolt/lib/Passes/PLTCall.cpp bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp bolt/lib/Target/X86/X86MCPlusBuilder.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/bolt/test/Inputs/plt-tailcall.c b/bolt/test/Inputs/plt-tailcall.c
index ebc04b2041..13f6e29c60 100644
--- a/bolt/test/Inputs/plt-tailcall.c
+++ b/bolt/test/Inputs/plt-tailcall.c
@@ -5,6 +5,4 @@ int foo(char *c) {
   __attribute__((musttail)) return puts(c);
 }
 
-int main() {
-  return foo("a");
-}
+int main() { return foo("a"); }

``````````

</details>


https://github.com/llvm/llvm-project/pull/93584