[llvm] Reland "[InstCombine] Fold (sub nuw X, (Y << nuw Z)) >>u exact Z --> (X >>u exact Z) sub nuw Y" (PR #93571)
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Tue May 28 09:43:42 PDT 2024
https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/93571
>From 4c648e321647ef73d6effc1b9b67bd3fff05d212 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Tue, 7 May 2024 15:29:07 -0400
Subject: [PATCH 1/4] [InstCombine] Pre-commit tests (NFC)
---
llvm/test/Transforms/InstCombine/lshr.ll | 28 ++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index fa92c1c4b3be4..ed303cf31f4ba 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -466,6 +466,34 @@ define i32 @shl_sub_lshr(i32 %x, i32 %c, i32 %y) {
ret i32 %lshr
}
+define i32 @shl_sub_lshr_reverse(i32 %x, i32 %c, i32 %y) {
+; CHECK-LABEL: @shl_sub_lshr_reverse(
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[X:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 [[Y:%.*]], [[SHL]]
+; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i32 [[SUB]], [[C]]
+; CHECK-NEXT: ret i32 [[LSHR]]
+;
+ %shl = shl nuw i32 %x, %c
+ %sub = sub nuw nsw i32 %y, %shl
+ %lshr = lshr exact i32 %sub, %c
+ ret i32 %lshr
+}
+
+; Negative test
+
+define i32 @shl_sub_lshr_reverse_no_exact(i32 %x, i32 %c, i32 %y) {
+; CHECK-LABEL: @shl_sub_lshr_reverse_no_exact(
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[X:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 [[Y:%.*]], [[SHL]]
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[SUB]], [[C]]
+; CHECK-NEXT: ret i32 [[LSHR]]
+;
+ %shl = shl nuw i32 %x, %c
+ %sub = sub nuw nsw i32 %y, %shl
+ %lshr = lshr i32 %sub, %c
+ ret i32 %lshr
+}
+
define i32 @shl_or_lshr(i32 %x, i32 %c, i32 %y) {
; CHECK-LABEL: @shl_or_lshr(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[Y:%.*]], [[C:%.*]]
>From cb81a07a3c499e06f1a429ba479d68dc6faa52ce Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Tue, 7 May 2024 15:30:01 -0400
Subject: [PATCH 2/4] [InstCombine] Fold (sub nuw X, (Y << nuw Z)) >>u exact Z
--> (X >>u exact Z) sub nuw Y
This is the same fold as ((X << nuw Z) sub nuw Y) >>u exact Z --> X sub nuw (Y >>u exact Z), but with the sub operands swapped.
Proof: https://alive2.llvm.org/ce/z/2cRcdx
---
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp | 11 +++++++++++
llvm/test/Transforms/InstCombine/lshr.ll | 5 ++---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index ba297111d945f..8d0209ccd13ef 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -1271,6 +1271,17 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
return NewSub;
}
+ // (sub nuw X, (Y << nuw Z)) >>u exact Z --> (X >>u exact Z) sub nuw Y
+ if (I.isExact() &&
+ match(Op0, m_OneUse(m_NUWSub(m_Value(X),
+ m_NUWShl(m_Value(Y), m_Specific(Op1)))))) {
+ Value *NewLshr = Builder.CreateLShr(X, Op1, "", /*isExact=*/true);
+ auto *NewSub = BinaryOperator::CreateNUWSub(NewLshr, Y);
+ NewSub->setHasNoSignedWrap(
+ cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap());
+ return NewSub;
+ }
+
auto isSuitableBinOpcode = [](Instruction::BinaryOps BinOpcode) {
switch (BinOpcode) {
default:
diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index ed303cf31f4ba..1e370d960c45d 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -468,9 +468,8 @@ define i32 @shl_sub_lshr(i32 %x, i32 %c, i32 %y) {
define i32 @shl_sub_lshr_reverse(i32 %x, i32 %c, i32 %y) {
; CHECK-LABEL: @shl_sub_lshr_reverse(
-; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[X:%.*]], [[C:%.*]]
-; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 [[Y:%.*]], [[SHL]]
-; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i32 [[SUB]], [[C]]
+; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[Y:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = sub nuw nsw i32 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[LSHR]]
;
%shl = shl nuw i32 %x, %c
>From bccac465c23e5451ebcb5b3c5fd7c89feb722146 Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Tue, 28 May 2024 12:31:58 -0400
Subject: [PATCH 3/4] Add no new test
---
llvm/test/Transforms/InstCombine/lshr.ll | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index 1e370d960c45d..84c06d729b72c 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -478,6 +478,19 @@ define i32 @shl_sub_lshr_reverse(i32 %x, i32 %c, i32 %y) {
ret i32 %lshr
}
+define i32 @shl_sub_lshr_reverse_no_nsw(i32 %x, i32 %c, i32 %y) {
+; CHECK-LABEL: @shl_sub_lshr_reverse_no_nsw(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[Y:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = sub nuw i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[LSHR]]
+;
+ %shl = shl nuw i32 %x, %c
+ %sub = sub nuw i32 %y, %shl
+ %lshr = lshr exact i32 %sub, %c
+ ret i32 %lshr
+}
+
+
; Negative test
define i32 @shl_sub_lshr_reverse_no_exact(i32 %x, i32 %c, i32 %y) {
>From 7e076b7b4e857a678af5eb8b02bc9e492010e768 Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Tue, 28 May 2024 12:43:33 -0400
Subject: [PATCH 4/4] Add nsw on op1, not op0 test
---
llvm/test/Transforms/InstCombine/lshr.ll | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index 84c06d729b72c..270b84772501d 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -490,6 +490,17 @@ define i32 @shl_sub_lshr_reverse_no_nsw(i32 %x, i32 %c, i32 %y) {
ret i32 %lshr
}
+define i32 @shl_sub_lshr_reverse_nsw_on_op1(i32 %x, i32 %c, i32 %y) {
+; CHECK-LABEL: @shl_sub_lshr_reverse_nsw_on_op1(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[Y:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = sub nuw i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[LSHR]]
+;
+ %shl = shl nuw nsw i32 %x, %c
+ %sub = sub nuw i32 %y, %shl
+ %lshr = lshr exact i32 %sub, %c
+ ret i32 %lshr
+}
; Negative test
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