[llvm] 17ecd23 - [X86][tablgen] Extend X86CompressEVEXTablesEmitter for NF transform
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Tue May 28 05:07:23 PDT 2024
Author: Shengchen Kan
Date: 2024-05-28T20:06:40+08:00
New Revision: 17ecd23f6932c87fcc8b2b8675762d50f3d53056
URL: https://github.com/llvm/llvm-project/commit/17ecd23f6932c87fcc8b2b8675762d50f3d53056
DIFF: https://github.com/llvm/llvm-project/commit/17ecd23f6932c87fcc8b2b8675762d50f3d53056.diff
LOG: [X86][tablgen] Extend X86CompressEVEXTablesEmitter for NF transform
The generated table will be used in #93508
Added:
llvm/utils/TableGen/X86InstrMappingEmitter.cpp
Modified:
llvm/lib/Target/X86/CMakeLists.txt
llvm/lib/Target/X86/X86CompressEVEX.cpp
llvm/utils/TableGen/CMakeLists.txt
Removed:
llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
################################################################################
diff --git a/llvm/lib/Target/X86/CMakeLists.txt b/llvm/lib/Target/X86/CMakeLists.txt
index 610999f0cc3cf..44a54c8ec62cb 100644
--- a/llvm/lib/Target/X86/CMakeLists.txt
+++ b/llvm/lib/Target/X86/CMakeLists.txt
@@ -8,7 +8,7 @@ tablegen(LLVM X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)
tablegen(LLVM X86GenDAGISel.inc -gen-dag-isel)
tablegen(LLVM X86GenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM X86GenCompressEVEXTables.inc -gen-x86-compress-evex-tables)
+tablegen(LLVM X86GenInstrMapping.inc -gen-x86-instr-mapping)
tablegen(LLVM X86GenExegesis.inc -gen-exegesis)
tablegen(LLVM X86GenFastISel.inc -gen-fast-isel)
tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp
index d2aa712772bfb..6442cc2193308 100644
--- a/llvm/lib/Target/X86/X86CompressEVEX.cpp
+++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp
@@ -50,27 +50,15 @@
using namespace llvm;
-// Including the generated EVEX compression tables.
-struct X86CompressEVEXTableEntry {
- uint16_t OldOpc;
- uint16_t NewOpc;
-
- bool operator<(const X86CompressEVEXTableEntry &RHS) const {
- return OldOpc < RHS.OldOpc;
- }
-
- friend bool operator<(const X86CompressEVEXTableEntry &TE, unsigned Opc) {
- return TE.OldOpc < Opc;
- }
-};
-#include "X86GenCompressEVEXTables.inc"
-
#define COMP_EVEX_DESC "Compressing EVEX instrs when possible"
#define COMP_EVEX_NAME "x86-compress-evex"
#define DEBUG_TYPE COMP_EVEX_NAME
namespace {
+// Including the generated EVEX compression tables.
+#define GET_X86_COMPRESS_EVEX_TABLE
+#include "X86GenInstrMapping.inc"
class CompressEVEXPass : public MachineFunctionPass {
public:
@@ -234,7 +222,7 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
if (IsNDLike && !isRedundantNewDataDest(MI, ST))
return false;
- ArrayRef<X86CompressEVEXTableEntry> Table = ArrayRef(X86CompressEVEXTable);
+ ArrayRef<X86TableEntry> Table = ArrayRef(X86CompressEVEXTable);
Opc = MI.getOpcode();
const auto *I = llvm::lower_bound(Table, Opc);
diff --git a/llvm/utils/TableGen/CMakeLists.txt b/llvm/utils/TableGen/CMakeLists.txt
index 6a0124dce4292..abebb98761d06 100644
--- a/llvm/utils/TableGen/CMakeLists.txt
+++ b/llvm/utils/TableGen/CMakeLists.txt
@@ -70,7 +70,7 @@ add_tablegen(llvm-tblgen LLVM
TableGen.cpp
VTEmitter.cpp
WebAssemblyDisassemblerEmitter.cpp
- X86CompressEVEXTablesEmitter.cpp
+ X86InstrMappingEmitter.cpp
X86DisassemblerTables.cpp
X86FoldTablesEmitter.cpp
X86MnemonicTables.cpp
diff --git a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
similarity index 68%
rename from llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
rename to llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index c721502a395f0..a8970d8bcbacd 100644
--- a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -1,4 +1,4 @@
-//==- utils/TableGen/X86CompressEVEXTablesEmitter.cpp - X86 backend-*- C++ -*-//
+//========- utils/TableGen/X86InstrMappingEmitter.cpp - X86 backend-*- C++ -*-//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
///
-/// This tablegen backend is responsible for emitting the X86 backend EVEX
-/// compression tables.
+/// This tablegen backend is responsible for emitting the X86 backend
+/// instruction mapping.
///
//===----------------------------------------------------------------------===//
@@ -34,7 +34,7 @@ const std::set<StringRef> NoCompressSet = {
#include "X86ManualCompressEVEXTables.def"
};
-class X86CompressEVEXTablesEmitter {
+class X86InstrMappingEmitter {
RecordKeeper &Records;
CodeGenTarget Target;
@@ -49,28 +49,58 @@ class X86CompressEVEXTablesEmitter {
typedef std::map<StringRef, std::vector<const CodeGenInstruction *>>
PredicateInstMap;
- std::vector<Entry> Table;
// Hold all compressed instructions that need to check predicate
PredicateInstMap PredicateInsts;
public:
- X86CompressEVEXTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
+ X86InstrMappingEmitter(RecordKeeper &R) : Records(R), Target(R) {}
// run - Output X86 EVEX compression tables.
void run(raw_ostream &OS);
private:
- // Prints the given table as a C++ array of type X86CompressEVEXTableEntry
- void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
- // Prints function which checks target feature for compressed instructions.
- void printCheckPredicate(const PredicateInstMap &PredicateInsts,
- raw_ostream &OS);
+ void emitCompressEVEXTable(ArrayRef<const CodeGenInstruction *> Insts,
+ raw_ostream &OS);
+ void emitNFTransformTable(ArrayRef<const CodeGenInstruction *> Insts,
+ raw_ostream &OS);
+
+ // Prints the definition of class X86TableEntry.
+ void printClassDef(raw_ostream &OS);
+ // Prints the given table as a C++ array of type X86TableEntry under the guard
+ // \p Macro.
+ void printTable(const std::vector<Entry> &Table, StringRef Name,
+ StringRef Macro, raw_ostream &OS);
};
-void X86CompressEVEXTablesEmitter::printTable(const std::vector<Entry> &Table,
- raw_ostream &OS) {
+void X86InstrMappingEmitter::printClassDef(raw_ostream &OS) {
+ OS << "struct X86TableEntry {\n"
+ " uint16_t OldOpc;\n"
+ " uint16_t NewOpc;\n"
+ " bool operator<(const X86TableEntry &RHS) const {\n"
+ " return OldOpc < RHS.OldOpc;\n"
+ " }"
+ " friend bool operator<(const X86TableEntry &TE, unsigned Opc) {\n"
+ " return TE.OldOpc < Opc;\n"
+ " }\n"
+ "};";
+
+ OS << "\n\n";
+}
+
+static void printMacroBegin(StringRef Macro, raw_ostream &OS) {
+ OS << "\n#ifdef " << Macro << "\n";
+}
+
+static void printMacroEnd(StringRef Macro, raw_ostream &OS) {
+ OS << "#endif // " << Macro << "\n\n";
+}
- OS << "static const X86CompressEVEXTableEntry X86CompressEVEXTable[] = {\n";
+void X86InstrMappingEmitter::printTable(const std::vector<Entry> &Table,
+ StringRef Name, StringRef Macro,
+ raw_ostream &OS) {
+ printMacroBegin(Macro, OS);
+
+ OS << "static const X86TableEntry " << Name << "[] = {\n";
// Print all entries added to the table
for (const auto &Pair : Table)
@@ -78,23 +108,8 @@ void X86CompressEVEXTablesEmitter::printTable(const std::vector<Entry> &Table,
<< ", X86::" << Pair.second->TheDef->getName() << " },\n";
OS << "};\n\n";
-}
-
-void X86CompressEVEXTablesEmitter::printCheckPredicate(
- const PredicateInstMap &PredicateInsts, raw_ostream &OS) {
-
- OS << "static bool checkPredicate(unsigned Opc, const X86Subtarget "
- "*Subtarget) {\n"
- << " switch (Opc) {\n"
- << " default: return true;\n";
- for (const auto &[Key, Val] : PredicateInsts) {
- for (const auto &Inst : Val)
- OS << " case X86::" << Inst->TheDef->getName() << ":\n";
- OS << " return " << Key << ";\n";
- }
- OS << " }\n";
- OS << "}\n\n";
+ printMacroEnd(Macro, OS);
}
static uint8_t byteFromBitsInit(const BitsInit *B) {
@@ -150,18 +165,19 @@ class IsMatch {
}
};
-void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
- emitSourceFileHeader("X86 EVEX compression tables", OS);
-
- ArrayRef<const CodeGenInstruction *> NumberedInstructions =
- Target.getInstructionsByEnumValue();
+static bool isInteresting(const Record *Rec) {
+ // _REV instruction should not appear before encoding optimization
+ return Rec->isSubClassOf("X86Inst") &&
+ !Rec->getValueAsBit("isAsmParserOnly") &&
+ !Rec->getName().ends_with("_REV");
+}
- for (const CodeGenInstruction *Inst : NumberedInstructions) {
+void X86InstrMappingEmitter::emitCompressEVEXTable(
+ ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
+ for (const CodeGenInstruction *Inst : Insts) {
const Record *Rec = Inst->TheDef;
StringRef Name = Rec->getName();
- // _REV instruction should not appear before encoding optimization
- if (!Rec->isSubClassOf("X86Inst") ||
- Rec->getValueAsBit("isAsmParserOnly") || Name.ends_with("_REV"))
+ if (!isInteresting(Rec))
continue;
// Promoted legacy instruction is in EVEX space, and has REX2-encoding
@@ -188,6 +204,7 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
PreCompressionInsts.push_back(Inst);
}
+ std::vector<Entry> Table;
for (const CodeGenInstruction *Inst : PreCompressionInsts) {
const Record *Rec = Inst->TheDef;
uint8_t Opcode = byteFromBitsInit(Rec->getValueAsBitsInit("Opcode"));
@@ -229,10 +246,53 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
PredicateInsts[(*It)->getValueAsString("CondString")].push_back(NewInst);
}
- printTable(Table, OS);
- printCheckPredicate(PredicateInsts, OS);
+ StringRef Macro = "GET_X86_COMPRESS_EVEX_TABLE";
+ printTable(Table, "X86CompressEVEXTable", Macro, OS);
+
+ // Prints function which checks target feature for compressed instructions.
+ printMacroBegin(Macro, OS);
+ OS << "static bool checkPredicate(unsigned Opc, const X86Subtarget "
+ "*Subtarget) {\n"
+ << " switch (Opc) {\n"
+ << " default: return true;\n";
+ for (const auto &[Key, Val] : PredicateInsts) {
+ for (const auto &Inst : Val)
+ OS << " case X86::" << Inst->TheDef->getName() << ":\n";
+ OS << " return " << Key << ";\n";
+ }
+ OS << " }\n";
+ OS << "}\n\n";
+ printMacroEnd(Macro, OS);
+}
+
+void X86InstrMappingEmitter::emitNFTransformTable(
+ ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
+ std::vector<Entry> Table;
+ for (const CodeGenInstruction *Inst : Insts) {
+ const Record *Rec = Inst->TheDef;
+ if (!isInteresting(Rec))
+ continue;
+ std::string Name = Rec->getName().str();
+ auto Pos = Name.find("_NF");
+ if (Pos == std::string::npos)
+ continue;
+
+ if (auto *NewRec = Records.getDef(Name.erase(Pos, 3)))
+ Table.push_back(std::pair(&Target.getInstruction(NewRec), Inst));
+ }
+ printTable(Table, "X86NFTransformTable", "GET_X86_NF_TRANSFORM_TABLE", OS);
+}
+
+void X86InstrMappingEmitter::run(raw_ostream &OS) {
+ emitSourceFileHeader("X86 instruction mapping", OS);
+
+ ArrayRef<const CodeGenInstruction *> Insts =
+ Target.getInstructionsByEnumValue();
+ printClassDef(OS);
+ emitCompressEVEXTable(Insts, OS);
+ emitNFTransformTable(Insts, OS);
}
} // namespace
-static TableGen::Emitter::OptClass<X86CompressEVEXTablesEmitter>
- X("gen-x86-compress-evex-tables", "Generate X86 EVEX compression tables");
+static TableGen::Emitter::OptClass<X86InstrMappingEmitter>
+ X("gen-x86-instr-mapping", "Generate X86 instruction mapping");
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