[llvm] [RFC][MC] Cache MCRegAliasIterator (PR #93510)

[Pierre van Houtryve via llvm-commits]

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@@ -726,60 +730,122 @@ class MCRegUnitRootIterator {
 /// MCRegAliasIterator enumerates all registers aliasing Reg.  If IncludeSelf is
 /// set, Reg itself is included in the list.  This iterator does not guarantee
 /// any ordering or that entries are unique.
+///
+/// This iterator can work in two modes: cached and uncached.
+///
+/// In Uncached mode, this uses RegUnit/RegUnitRoot/SuperReg iterators to
+/// find all aliases. This is very expensive if the target (such as AMDGPU)
+/// has a lot of register and register aliases. It can also cause us
+/// to iterate the same register many times over.
+///
+/// In cached mode, the iterator requests MCRegisterInfo for a cache.
+/// MCRegisterInfo then returns a cached list of sorted, uniqued
+/// aliases for that register. This allows the iterator to be faster
+/// past the first request, but also to iterate much less in some
+/// cases, giving a slight speedup to any code that's using it.
 class MCRegAliasIterator {
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Pierre-vh wrote:

I'm wondering if I should move the old implementation to a `MCRegAliasIteratorUncached` class, and then make `MCRegAliasIterator` the default cached implementation.

It makes things a bit cleaner (and makes the caching system easier to remove someday), but makes it very difficult to add a cache "killswitch" if we feel like one is necessary (like if we don't want caching on all targets).

https://github.com/llvm/llvm-project/pull/93510