[llvm] [RISCV] Support Inline ASM for the bf16 type. (PR #80118)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zfbfmin -target-abi=ilp32 -verify-machineinstrs < %s \
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arsenm wrote:

Don't need all the -verify-machineinstrs 

https://github.com/llvm/llvm-project/pull/80118