[llvm] [AArch64][GISel] Support SVE with 128-bit min-size for G_LOAD and G_STORE (PR #92130)

David Green via llvm-commits llvm-commits at lists.llvm.org
Tue May 28 02:18:15 PDT 2024


================
@@ -329,6 +335,20 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
     return ValTy.isPointerVector() && ValTy.getAddressSpace() == 0;
   };
 
+  if (ST.hasSVE()) {
+    for (const auto OpCode : {G_LOAD, G_STORE}) {
+      getActionDefinitionsBuilder(OpCode)
+      .legalForTypesWithMemDesc({
+        // 128 bit base sizes
+        {nxv16s8, p0, nxv16s8, 128},
----------------
davemgreen wrote:

Yeah 8 should be fine. SDAG seems to accept the smaller alignments.

https://github.com/llvm/llvm-project/pull/92130


More information about the llvm-commits mailing list