[llvm] [WIP][AMDGPU] Optimized SGPR spills into VGPR lanes for non-interfering spill regions. (PR #93506)

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``````````bash
git-clang-format --diff 42c4027729ac7dbfb732a361ab8085d4af0a7a0a cd10c35389d057686f499f8f9233ffbaf702e198 -- llvm/lib/CodeGen/StackSlotColoring.cpp llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp
index d655fc4e08..00cc6e60a1 100644
--- a/llvm/lib/CodeGen/StackSlotColoring.cpp
+++ b/llvm/lib/CodeGen/StackSlotColoring.cpp
@@ -155,9 +155,10 @@ namespace {
       AU.addPreserved<MachineBlockFrequencyInfo>();
       AU.addPreservedID(MachineDominatorsID);
 
-      /// NOTE: As in AMDGPU pass pipeline, reg alloc is spillted into 2 phases and StackSlotColoring is invoked 
-      /// after each phase, it becomes important to preserve additional analyses result to be used by VGPR regAlloc, 
-      /// after being done with SGPR regAlloc and its related passes. 
+      /// NOTE: As in AMDGPU pass pipeline, reg alloc is spillted into 2 phases
+      /// and StackSlotColoring is invoked after each phase, it becomes
+      /// important to preserve additional analyses result to be used by VGPR
+      /// regAlloc, after being done with SGPR regAlloc and its related passes.
       AU.addPreserved<LiveIntervals>();
       AU.addPreserved<LiveDebugVariables>();
 

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https://github.com/llvm/llvm-project/pull/93506