[llvm] [RISCV] Support Inline ASM for the bf16 type. (PR #80118)

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git-clang-format --diff 698058fd2bcbe9966f56eb132ae8741cd89f1048 daa224ad73986ca8788fbe4c988132ce07e9be24 -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f5708f6266..20f3c45a16 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20274,7 +20274,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         unsigned HReg = RISCV::F0_H + RegNo;
         return std::make_pair(HReg, &RISCV::FPR16RegClass);
       }
-      if (Subtarget.hasStdExtZfbfmin() && VT == MVT::bf16){
+      if (Subtarget.hasStdExtZfbfmin() && VT == MVT::bf16) {
         unsigned RegNo = FReg - RISCV::F0_F;
         unsigned HReg = RISCV::F0_H + RegNo;
         return std::make_pair(HReg, &RISCV::FPR16RegClass);
@@ -20958,7 +20958,7 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
   // Since the inline asm only use the first type in the RegisterClass, the bf16
   // inline asm would choose the f16 from FPR16RegClass for doing the copy, and
   // we correct the behavior here to avoid generating wrong SelectionDAG.
-  if (ValueVT == MVT::bf16 && PartVT == MVT::f16){
+  if (ValueVT == MVT::bf16 && PartVT == MVT::f16) {
     Parts[0] = Val;
     return true;
   }

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https://github.com/llvm/llvm-project/pull/80118