[llvm] [MachineScheduler][ScheduleDAG] Add ability to bias scheduling by longest paths (PR #93223)

[Michael Maitland via llvm-commits]

michaelmaitland wrote:

> Make sense to me, I just wonder how this change would improve dynamic inst counts, does this change decrease register pressure in some way?

I did some more experiments. It turns out that the dynamic IC actually stays the same as a result of this change. All diff in spec2006 and spec2017 is related to reordering of instructions.

https://github.com/llvm/llvm-project/pull/93223